Semiconductor memory device having a plurality of signal lines for writing and reading data
View Patent ↗A write-driver/read-amplifier circuit includes a write driver, a GIO equalize circuit and a read amplifier. When a current leaks from or to global data line, a signal applied to a logic gate attains L-level. As a result, the write driver and the GIO equalize circuit stop the operations so that a semiconductor memory device can prevent occurrence of an unnecessary leak current.
1. A semiconductor memory device having a test mode, comprising:
a memory cell array including a plurality of memory cells;
a plurality of signal lines for selecting a specific memory cell from said plurality of memory cells and operating to write and read data;
a test signal generating circuit generating a test signal in said test mode;
a potential supply circuit supplying a predetermined potential to said plurality of signal lines in response to said test signal;
a determining circuit determining whether said plurality of signal lines hold said predetermined potential or not;
a determination control circuit connected between said plurality of signal lines and said determining circuit, said determination control circuit for selectively connecting said signal lines to said determining circuit in response to said test signal; and
a determination result storage circuit storing a result of the determination by said determining circuit.
2. The semiconductor memory device according to claim 1 , wherein
said determination result storage circuit includes:
a storage circuit storing said result of the determination in response to said test signal; and
a determination result reading circuit externally outputting said result of the determination stored in said storage circuit in response to said test signal.
3. The semiconductor memory device according to claim 1 , wherein
said predetermined potential is an external power supply potential.
4. The semiconductor memory device according to claim 1 , wherein
said predetermined potential is a ground potential.
5. A semiconductor memory device having a test mode, comprising:
a memory cell array including a plurality of memory cells;
a plurality of signal lines for selecting a specific memory cell from said plurality of memory cells and operating to write and read data;
a test signal generating circuit generating a test signal in said test mode;
a potential supply circuit supplying a predetermined potential to said plurality of signal lines in response to said test signal; and
a determining circuit determining whether said plurality of signal lines hold said predetermined potential or not; wherein
said potential supply circuit includes:
a driver including a first transistor connected between a power supply node and an output node connected to said signal line, and having a gate receiving a first signal, and a second transistor connected between said output node and a ground node, and having a gate receiving a second signal complementary to said first signal; and
a transistor forced operation circuit selectively turning on said first and second transistors in response to said test signal.