Non-volatile memory device
View Patent ↗A non-volatile memory device is provided by forming a tunnel oxide layer and a gate electrode on the tunnel oxide layer. Silicon structures are formed below the side surfaces of the gate electrode and act as a floating gate electrode for the non-volatile memory device.
1. A memory device, comprising:
a semiconductor substrate comprising a channel region, a source region and a drain region;
a gate electrode having an upper surface and side surfaces;
a dielectric layer formed on an upper surface of the semiconductor substrate, the dielectric layer extending laterally below the gate electrode; and
silicon structures formed within a portion of the dielectric layer and located between the semiconductor substrate and each of the side surfaces of the gate electrode, the silicon structures extending laterally below a portion of the gate electrode, wherein the silicon structures act as a floating gate electrode for the memory device and a thickness of the dielectric layer located between the semiconductor substrate and the silicon structures is less than a thickness of the dielectric layer located between the silicon structures and the gate electrode.
2. The memory device of claim 1 , wherein the silicon structures comprise first and second structures, the first structure extending laterally below a first one of the side surfaces of the gate electrode and the second structure extending laterally below a second one of the side surfaces of the gate electrode.
3. The memory device of claim 2 , wherein each of the first and second structures comprise a continuous polysilicon structure below each of the respective side surfaces of the gate electrode.
4. The memory device of claim 1 , wherein the silicon structures comprise a plurality of discontinuous pockets of polysilicon, the plurality of discontinuous pockets of polysilicon together storing a charge that may be read.
5. The memory device of claim 1 , wherein a portion of the dielectric layer located between the semiconductor substrate and the gate electrode comprises a tunnel oxide.
6. The memory device of claim 1 , wherein the dielectric layer extends over the upper and side surfaces of the gate electrode, the memory device further comprising:
nitride sidewall spacers formed adjacent a portion of the dielectric layer that extends over the side surfaces of the gate electrode.
7. A memory device, comprising:
a semiconductor substrate comprising a channel region, a source region and a drain region;
a gate electrode;
a dielectric layer formed on an upper surface of the semiconductor substrate, the dielectric layer extending laterally below the gate electrode; and
silicon structures formed within the dielectric layer, the silicon structures extending laterally below a portion of the gate electrode, wherein the silicon structures act as a floating gate electrode for the memory device and have a cross-sectional size of about 50 Å in length and 20 Å in heights, wherein a thickness of the dielectric layer located between the semiconductor substrate and the silicon structures is less than a thickness of the dielectric layer located between the silicon structures and the gate electrode.
8. A memory device, comprising:
a semiconductor substrate comprising a channel region, a source region and a drain region;
a gate electrode having an upper surface and side surfaces;
a dielectric layer formed on an upper surface of the semiconductor substrate, the dielectric layer extending laterally below the gate electrode; and
silicon structures formed within a portion of the dielectric layer and located between the semiconductor substrate and the side surfaces of the gate electrode, the silicon structures extending laterally below a portion of the gate electrode, wherein the silicon structures act as a floating gate electrode for the memory device and have a teardrop-like shape.
9. A non-volatile memory device, comprising:
a semiconductor substrate comprising a channel region, a source region and a drain region;
a gate electrode having an upper surface and side surfaces;
a tunnel oxide layer formed on an upper surface of the semiconductor substrate below the gate electrode; and
a quantum well formed in the tunnel oxide layer, wherein the quantum well acts as a floating gate electrode for the non-volatile memory device and a thickness of the tunnel oxide layer located between the substrate and the quantum well is less than a thickness of the tunnel oxide layer located between the quantum well and the gate electrode.
10. The non-volatile memory device of claim 9 , wherein the quantum well comprises a number of polysilicon structures formed in at least one of a continuous or discontinuous manner below the side surfaces of the gate electrode.
11. The non-volatile memory device of claim 9 , wherein the channel region comprises silicon doped with p-type impurities and the source and drain regions comprise silicon doped with n-type impurities.
12. The non-volatile memory device of claim 9 , further comprising:
an oxide layer formed over the upper and side surfaces of the gate electrode; and
nitride sidewall spacers formed adjacent a portion of the oxide layer that extends over the side surfaces of the gate electrode.
13. The non-volatile memory device of claim 10 , wherein the number of polysilicon structures are formed in a discontinuous manner and together store a charge that may be read.
14. The non-volatile memory device of claim 9 , wherein the quantum well has a teardrop-like cross-sectional shape.
15. The non-volatile memory device of claim 9 , wherein the quantum well has a cross-sectional area of about 1000 square angstroms.
16. A non-volatile memory device, comprising:
a semiconductor substrate comprising a channel region, a source region and a drain region;
a gate electrode having an upper surface and side surfaces;
a tunnel oxide layer formed on an upper surface of the semiconductor substrate below the gate electrode; and
a quantum well having a teardrop-like cross-sectional shape formed in the tunnel oxide layer, wherein the quantum well acts as a floating gate electrode for the non-volatile memory device.
17. A semiconductor device, comprising:
a channel region;
a source region;
a drain region;
a control gate;
a dielectric layer formed on an upper surface of the semiconductor substrate, the dielectric layer extending laterally below the control gate; and
at least one silicon structure formed within the dielectric layer, the at least one silicon structure acting as a charge storage element for the semiconductor device and wherein a first portion of the at least one silicon structure extends directly below the control gate and a second portion of the at least one silicon structure does not extend directly below the control gate.
18. The semiconductor device of claim 17 , wherein the at least one silicon structure has a teardrop-like cross-sectional shape.
19. The semiconductor device of claim 17 , wherein a thickness of the dielectric layer located between the semiconductor substrate and the at least one silicon structure is less than a thickness of the dielectric layer located between the at least one silicon structure and the control gate.
20. The semiconductor device of claim 17 , wherein the at least one silicon structure comprises more than two silicon structures that together store a charge that can be read.