Self-aligned vertical gate semiconductor device
View Patent ↗A transistor ( 10 ) is formed in a semiconductor substrate ( 12 ) whose top surface ( 48 ) is formed with a pedestal structure ( 24 ). A conductive material ( 40 ) is disposed along a side surface ( 28 ) of the pedestal structure to self-align an edge of a first conduction electrode ( 45 ) of the transistor. A dielectric spacer ( 55 ) is formed along a side surface ( 49 ) of the conductive material to self-align a contact area ( 56 ) of the first conduction electrode.
1. A transistor ( 10 ), comprising:
a substrate ( 12 ) having a top surface ( 48 ) for forming a pedestal structure ( 24 );
a conductive material ( 40 ) disposed along a side surface ( 28 ) of the pedestal structure to define an edge of a first conduction electrode ( 45 ) within the substrate; and
a dielectric spacer ( 55 ) formed along a side surface ( 49 ) of the conductive material to define a contact area ( 56 ) of the first conduction electrode.
2. The transistor of claim 1 , wherein the substrate includes:
a semiconductor layer ( 14 , 16 ); and
a first dielectric layer ( 18 ) formed over the semiconductor layer to support the pedestal structure, the conductive material and the dielectric spacer.
3. The transistor of claim 2 , wherein a side surface of the dielectric spacer defines an opening in the first dielectric layer that exposes the semiconductor layer to form the contact area.
4. The transistor of claim 1 , wherein the substrate is formed with a body region ( 31 ) having an edge ( 33 ) defined by the side surface of the pedestal structure.
5. The transistor of claim 4 , wherein the conductive material inverts the body region to form a channel ( 50 ) at the top surface of the substrate.
6. The transistor of claim 5 , further comprising a second conduction electrode ( 14 , 64 ) of the transistor formed at a bottom surface ( 63 ) of the substrate.
7. The transistor of claim 1 , wherein the pedestal structure includes:
a second dielectric layer ( 19 ) formed on the top surface of the substrate;
a third dielectric layer ( 20 ) formed on the second dielectric layer; and a
conductive layer ( 21 ) formed with the conductive material on the third dielectric layer.
8. The transistor of claim 7 , wherein the second dielectric layer includes silicon nitride.
9. The transistor of claim 7 , wherein the third dielectric layer includes silicon dioxide.
10. The transistor of claim 7 , wherein the conductive material includes polycrystalline silicon.
11. The transistor of claim 7 , wherein the second dielectric layer has a horizontal surface adjacent to the top surface of the substrate and a vertical surface ( 32 ) recessed from a vertical surface of the second dielectric layer.
12. The transistor of claim 11 , wherein the conductive material extends to the vertical surface of the second dielectric layer.
13. A semiconductor device ( 10 ), comprising:
a substrate ( 12 ) having a top surface ( 48 ) for doping a source region ( 45 ) within the substrate and forming a channel ( 50 ) of the semiconductor device;
a dielectric pedestal ( 19 , 20 ) formed on the top surface;
a control electrode ( 40 ) formed along a side surface ( 28 ) of the dielectric pedestal to define an edge of the source region; and
a dielectric spacer ( 55 ) formed along a side surface ( 49 ) of the control electrode to define a contact area ( 56 ) of the source region.
14. The semiconductor device of claim 13 , wherein the control electrode is extended over the dielectric pedestal to receive an external signal (V G ).
15. The semiconductor device of claim 13 , wherein the dielectric spacer is formed with silicon dioxide.
16. A semiconductor device ( 10 ), comprising:
a substrate ( 12 );
a first conductive material ( 40 ) disposed on a first surface ( 28 ) to define a conduction electrode ( 45 ) of the semiconductor device within the substrate and at a second surface ( 48 ) perpendicular to the first surface;
a dielectric spacer ( 55 ) formed on a surface ( 49 ) of the first conductive material that runs parallel to the first surface to define a contact area ( 56 ) of the conduction electrode.
17. The semiconductor device of claim 16 , further comprising:
a semiconductor substrate ( 12 ) for providing the first surface; and
a pedestal structure ( 24 ) disposed on the first surface and providing the second surface perpendicular to the first surface.
18. The semiconductor device of claim 17 , wherein the pedestal structure includes a nitride layer ( 19 ) and a conductive layer ( 21 ) formed over the nitride layer for electrically contacting the conductive material.
19. The semiconductor device of claim 16 , wherein the dielectric spacer is formed with silicon dioxide.
20. The semiconductor device of claim 16 , wherein the conductive material comprises polycrystalline silicon.