Granted Patent
Utility
US 6,642,145
· Confirmation No. 5192
METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT WITH DIELECTRIC DIFFUSION BARRIER LAYER FORMED BETWEEN INTERCONNECTS AND INTERLAYER DIELECTRIC LAYERS
Patented Case
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2003-08-04 | IFEE |
Issue Fee Payment (PTO-85B) | 1 | View | |
| 2003-08-04 | LET. |
Miscellaneous Incoming Letter | 2 | View | |
| 2002-08-22 | TRNA |
Transmittal of New Application | 2 | View | |
| 2002-08-22 | ADS |
Application Data Sheet | 2 | View | |
| 2002-08-22 | SPEC |
Specification | 9 | View | |
| 2002-08-22 | CLM |
Claims | 3 | View | |
| 2002-08-22 | ABST |
Abstract | 1 | View | |
| 2002-08-22 | DRW |
Drawings-only black and white line drawings | 2 | View | |
| 2002-08-22 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Attorneys & Agents of Record
Classification
USPC
438/639
H10W20/48
H10W20/425
H10W20/032
H10W20/096
H10W20/081
H10W20/076
Prosecution
- Examiner
- SMOOT, STEPHEN W
- Art Unit
- 2813
- Customer No.
- 22898
- Docket No.
- F0361.C1
- Confirmation No.
- 5192
Patent Term Adjustment
0days
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2021-03-30
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2018-01-31
SECURITY INTEREST
Recorded 2018-01-30
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Quick Facts
- Patent No.
- US 6,642,145
- App. No.
- 10/226,520
- Filed
- 2002-08-22
- Granted
- 2003-11-04
- Examiner
- SMOOT, STEPHEN W
- Art Unit
- 2813
- PTA
- 0 days
External Links