Multi-bit silicon nitride charge-trapping non-volatile memory cell
View Patent ↗A non-volatile multi-bit memory cell is presented which comprises a source, a drain, a channel coupling the source and the drain, and a gate with a plurality of charge trapping regions located so that a trapped charge in each charge trapping region is enabled to affect the influence of the gate voltage on the flow of electrons in the channel. The charge trapping regions are in multiple layers of oxide/nitride/oxide and there can be multiple levels of charge trapping regions. Charges are stored in the nitride layers and isolated by the oxide layers.
1. A non-volatile multi-bit memory cell, comprising:
a source;
a channel coupled to said source;
a drain coupled to said channel;
a gate coupled to said source and said drain, said gate disposed so as to affect electrical flow in said channel;
a first charge trapping layer vertically disposed over said channel that is capable of trapping two charges for affecting the influence of said gate on said electrical flow in said channel; and
a second charge trapping layer vertically disposed over said first charge trapping layer that is capable of trapping two charges for affecting the influence of said gate on said electrical flow in said channel.
2. The non-volatile multi-bit memory cell of claim 1 , further comprising:
a third charge trapping layer vertically disposed over said second charge trapping layer that is capable of trapping two charges for affecting the influence of said gate on said electrical flow in said channel.
3. The non-volatile multi-bit memory cell of claim 1 , wherein said memory cell is implemented as a mirror-bit cell.
4. The non-volatile multi-bit memory cell of claim 1 , wherein said first charge trapping layer comprises:
a first layer of oxide vertically disposed over said channel;
a first layer of nitride vertically disposed over said first layer of oxide; and
a second layer of oxide vertically disposed over said first layer of nitride.
5. The non-volatile multi-bit memory cell of claim 4 , wherein said second charge trapping layer comprises:
said second layer of oxide;
a second layer of nitride vertically disposed over said second layer of oxide; and
a third layer of oxide vertically disposed over said second layer of nitride.
6. The non-volatile multi-bit memory cell of claim 5 , wherein said first, second, and third layers of oxide are comprised of an oxide of silicon.
7. The non-volatile multi-bit memory cell of claim 5 , wherein said first and second layers of nitride are comprised of a nitride of silicon.
8. The non-volatile multi-bit memory cell of claim 1 , wherein said first and second charge trapping layers differ in programming voltage level.
9. The non-volatile multi-bit memory cell of claim 1 , wherein said first and second charge trapping layers differ in erasing voltage level.