Bitline equalization system for a DRAM integrated circuit
View Patent ↗A system for pre-charging and equalizing potentials on a bitline pair in a DRAM integrated circuit. The system includes an equalization circuit at one position on the bitline pair and another equalization circuit at another position on the bitline pair. As charge is distributed between the bitlines and to/from the pre-charge potential source through multiple conduction paths, the pre-charge and equalization time of the bitlines is reduced.
1. A bitline equalization system for pre charging a bitline and a complementary bitline to an equalization potential in a DRAM integrated circuit, the bitline equalization system comprising:
a first equalization circuit connected between a first position along the bitline and a corresponding first position along the complementary bitline, including
a first transistor having a first gate connected to a first equalization line, a first source connected to the first position along the bitline, and a first drain connected to the corresponding first position along the complementary bitline,
a second transistor having a second gate connected to the first equalization line, a second source connected to the first position along the bitline, and a second drain connected to the equalization potential,
a third transistor having a third gate connected to the first equalization line, a third source connected to the corresponding first position along the complementary bitline, and a third drain connected to the equalization potential; and
a second equalization circuit connected between a second position along the bitline and a corresponding second position along the complementary bitline, the second equalization circuit including a fourth transistor having a fourth gate connected to a second equalization line, a fourth source connected to the second position alone the bitline, and a fourth drain connected to the corresponding second position on the complementary bitline,
a fifth transistor having a fifth gate connected to the second equalization line, a fifth source connected to the second position along the bitline, and a fifth drain connected to the equalization potential; and
a sixth transistor having a sixth gate connected to the second equalization line, a sixth source connected to the corresponding second position along the complementary bitline, and a sixth drain connected to the equalization potential,
wherein the first position is closer to a beginning of the bitline than the second position, and wherein the first complementary position is closer to a beginning of the complementary bitline than the second complementary position.
2. The bitline equalization system of claim 1 , wherein the first equalization line and the second equalization line are a shared common equalization line.
3. The bitline equalization system of claim 1 , wherein the first position along the bitline is the beginning of the bitline and the corresponding first position along the complementary bitline is the beginning of the complementary bitline.
4. The bitline equalization system of claim 1 , wherein the second position along the bitline is an end of the bitline and the corresponding second position along the complementary bitline is an end of the complementary bitline.
5. The bitline equalization system of claim 1 , wherein the distance between the second position along the bitline and an end of the bitline is substantially the same as the distance between the first position along the bitline and a beginning of the bitline, and wherein the distance between the second complementary position along the complementary bitline and an end of the complementary bitline is substantially the same as the distance between the first complementary position along the complementary bitline and a beginning of the complementary bitline.
6. A bitline equalization system for pre charging a bitline and a complementary bitline to an equalization potential in a DRAM integrated circuit, the bitline equalization system comprising:
means for exchanging charge between the bitline and an equalization potential at a first position along the bitline;
means for exchanging charge between the complementary bitline and the equalization potential at a corresponding first position along the complementary bitline; and
means for exchanging charge between a second position along the bitline and a corresponding second position along the complementary bitline, wherein the first position is closer to a beginning of the bitline than the second position,
wherein the first complementary position is closer to a beginning of the complementary bitline than the second complementary position;
means for exchanging charge between the bitline and the equalization potential at the second position on the bitline; and
means for exchanging charge between the complementary bitline and the equalization potential at a corresponding second position on the complementary bitline.
7. The bitline equalization system of claim 6 , further comprising:
means for exchanging charge between the first position on the bitline and the corresponding first position on the complementary bitline.
8. A bitline equalization system for pre charging a bitline and a complementary bitline to an equalization potential in a DRAM integrated circuit, the bitline equalization system comprising:
a first transistor having a first gate connected to a common equalization line, a first source connected to the first position along the bitline, and a first drain connected to the corresponding first position along the complementary bitline;
a second transistor having a second gate connected to the common equalization line, a second source connected to the first position along the bitline, and a second drain connected to the equalization potential;
a third transistor having a third gate connected to the common equalization line, a third source connected to the corresponding first position along the complementary bitline, and a third drain connected to the equalization potential;
a fourth transistor having a fourth gate connected to the common equalization line, a fourth source connected to the second position along the bitline, and a fourth drain connected to the corresponding second position along the complementary bitline, wherein the first position is closer to a beginning of the bitline than the second position, and wherein the first complementary position is closer to a beginning of the complementary bitline than the second complementary position;
a fifth transistor having a fifth gate connected to the common equalization line, a fifth source connected to the second position along the bitline, and a fifth drain connected to the equalization potential; and
a sixth transistor having a sixth gate connected to the common equalization line, a sixth source connected to the corresponding second position along the complementary bitline, and sixth drain connected to the equalization potential.
9. A bitline equalization system for pre charging a bitline and a complementary bitline to an equalization potential in a DRAM integrated circuit, the bitline equalization system comprising:
a first equalization circuit connected between a first position along the bitline and a corresponding first position along the complementary bitline; and
a second equalization circuit connected between a second position along the bitline and a corresponding second position along the complementary bitline, wherein the first position is closer to a beginning of the bitline than the second position, and wherein the first complementary position is closer to a beginning of the complementary bitline than the second complementary position,
wherein the distance between the second position along the bitline and an end of the bitline is substantially the same as the distance between the first position along the bitline and a beginning of the bitline, and wherein the distance between the second complementary position along the complementary bitline and an end of the complementary bitline is substantially the same as the distance between the first complementary position along the complementary bitline and a beginning of the complementary bitline.