On-die detection of the system operation frequency in a DRAM to adjust DRAM operations
View Patent ↗The present invention relates to a memory system including an external clock and a memory chip connected to the external clock. The external clock generates an operating signal at an operating frequency that controls at least one electrical component of the memory system. The memory chip includes a frequency detector that detects at least a range of frequency values for the operating frequency. Further, the frequency detector includes a reference frequency generator that generates a reference signal at a reference frequency.
1. A memory system, comprising:
a external clock generating an operating signal at an operating frequency, said operating signal controlling at least one electrical component of said memory system; and
a memory chip connected to said external clock, wherein said memory chip comprises a frequency detector for detecting at least a range of frequency values for said operating frequency;
wherein said frequency detector comprises a reference frequency generator that generates a first reference signal at a first reference frequency.
2. The memory system of claim 1 , wherein said memory chip is a DRAM memory chip.
3. The memory system of claim 1 , wherein said memory chip is a SDRAM memory chip.
4. The memory system of claim 1 , wherein said memory chip is a DDR SDRAM memory chip.
5. The memory system of claim 1 , wherein said frequency detector comprises a comparator that receives said operating signal and said first reference signal and compares said range of frequency values of said operating frequency to a frequency value of said first reference frequency.
6. The memory system of claim 5 , wherein said frequency detector determines said range of frequency values for said operating frequency.
7. The memory system of claim 5 , wherein said frequency detector comprises:
a first counter that counts a first number of cycles of said operating signal over a first period of time; and
second counter that counts a second number of cycle of said first reference signal over a second period of time.
8. The memory system of claim 1 , wherein said frequency detector comprises a second reference frquency generator that generates a second reference signal at a second reference frequency.
9. The memory system of claim 8 , wherein said frequency detector comprises a comparator system that receives said operating signal, said first reference signal and said second reference signal and compares the value of said operating frequency with both said first reference frequency and said second reference frequency.
10. The memory system of claim 9 , wherein said comparator system determines a first range of values based on a comparison of the value of said operating frequency with said first reference frequency and a second range of values based on a comparison of the value of said operating frequency with said second reference frequency.
11. The memory system of claim 10 , wherein said range of values for said operating frewuency is the range of values defined as the overlap of said first and second range of values.
12. The memory system of claim 9 , wherein said frequency detector determines a range of values for said operating frequency.
13. The memory system of claim 9 , wherein said frequency detector determines a range of values for said operating frequency.
a first counter that counts a first number of cycles of said operating signal over a first period of time;
a second counter that counts a second number of cycle of said first reference signal over a second period of time.
a thrid counter that counts a third number of cycles of said second reference signal over a third period of time.