Multiple channel adaptive data recovery system
View Patent ↗A microprocessor controlled data recovery unit with an adjustable sampling and signal comparison level. The data recovery unit includes a data channel and a monitor channel. The monitor channel samples an incoming data stream in a varying manner. The results of the sampling in the monitor channel are used to adjust the sampling and comparing of the signal in the data channel. The data recovery unit includes a PLL based clock recovery unit in one embodiment, and in another embodiment the clock signal is derived by the microprocessor.
1. A method of determining a data rate comprising:
providing a data stream to a phase locked loop (PLL) including an oscillator having a plurality of ranges;
setting the oscillator to a first range;
determining if the PLL locks to a potential data rate of the data stream;
measuring for a data eye within a data cell defined by the potential data rate; and
setting the oscillator to a second range if the measurements for the data eye are inconsistent with an expected data eye for the potential data rate.
2. The method of claim 1 wherein measuring for a data eye within a data cell defined by the potential data rate comprises:
sampling the data stream at the potential data rate, the sampling occurring at a constant phase;
sampling the data stream at the potential data rate, the sampling occurring at a variable phase; and p 1 comparing the results of the sampling at the constant phase with the sampling at the variable phase for common data cells.
3. The method of claim 1 wherein determining if the PLL locks to a potential data rate of the data stream comprises determining if a loop bias filter voltage is approximately constant over time.
4. The method of claim 1 wherein determining if the PLL locks to a potential data rate of the data stream comprises determining if a loop bias filter voltage is within a specified range.
5. The method of claim 4 wherein determining if a loop bias filter voltage is within a specified range comprises examining a register indicating status of the loop bias filter voltage.
6. The method of claim 5 wherein the register includes a bit indicating that the loop bias filter voltage exceeds a specified voltage and a bit indicating that the loop bias filter voltage is below a specified voltage.
7. The method of claim 1 wherein measuring for a data eye within a data cell defined by the potential data rate comprises comparing data sampled at the potential data rate with approximately zero phase offset with data sampled at the potential data rate with approximately 180 degree phase offset.
8. The method of claim 7 wherein measurements for the data eye are inconsistent with an expected data eye for the potential data rate if results of the comparison of data sampled at the potential data rate with approximately zero phase offset with data sampled at the potential data rate with approximately 180 degree phase offset does not indicate appreciable differences.
9. The method of claim 8 wherein appreciable differences are differences in approximately 50 percent of compared bits.
10. A method of determining a data rate comprising:
providing a data stream to a clock recovery circuit;
determining, using the clock recovery circuit, a proposed data rate for the data stream;
providing the data stream to a channel;
sampling, the data stream on the channel at the proposed data rate;
changing the phase of the sampling with respect to a clock signal at the proposed data rate;
determining whether data transition boundaries for the data stream are in accordance with the proposed data rate; and
wherein determining whether data transition boundaries for the data stream are in accordance with the proposed data rate comprises determining if bit error rates increase at expected data transition boundaries.
11. A method of determining a data rate comprising:
providing a data stream to a clock recovery circuit;
determining, using the clock recovery circuit, a proposed data rate for the data stream;
providing the data stream to a channel;
sampling, the data stream on the channel at the proposed data rate;
changing the phase of the sampling with respect to a clock signal at the proposed data rate;
determining whether data transition boundaries for the data stream are in accordance with the proposed data rate; and
wherein determining whether data transition boundaries for the data stream are in accordance with the proposed data rate comprises determining if differences between data sampled at zero phase offset and data sampled at 180 degree phase offset are significant.
12. A method of determining a data rate comprising:
providing a data stream to a clock recovery circuit;
determining, using the clock recovery circuit, a proposed data rate for the data stream;
providing the data stream to a channel;
sampling, the data stream on the channel at the proposed data rate;
changing the phase of the sampling with respect to a clock signal at the proposed data rate;
determining whether data transition boundaries for the data stream are in accordance with the proposed data rate;
wherein determining whether data transition boundaries for the data stream are in accordance with the proposed data rate comprises determining a differential error count; and
wherein the differential error count is the difference between error counts for a zero phase offset and a 180 degree phase offset.