IP Library Granted Patent US 7,439,141
Granted Patent B2
US 7,439,141 · App. 10/277,395 · Granted Oct 21, 2008

Shallow trench isolation approach for improved STI corner rounding

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Quick Facts
Patent No.
US 7,439,141
App. No.
10/277,395
Granted
Oct 21, 2008
Kind
B2
Abstract

A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches into a silicon substrate between active regions, and performing a double liner oxidation process on the trenches. The method further includes performing a double sacrificial oxidation process on the active regions, wherein corners of the trenches are substantially rounded by the four oxidation processes.

Claims (26)

1. A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding, the method comprising the steps of:

(a) etching trenches into a silicon substrate between active regions;

(b) performing a double liner oxidation process on the trenches; and

(c) performing a double sacrificial oxidation process on the active regions, wherein corners of the trenches are rounded in each of the four oxidation processes.

2. A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding, the method comprising the steps of:

(a) etching trenches into a silicon substrate between active regions;

(b) performing a double liner oxidation process on the trenches; and

(c) performing a double sacrificial oxidation process on the active regions, wherein corners of the trenches are rounded in each of the four oxidation processes, wherein the silicon substrate includes a layer of pad oxide and a masking material that defines actives regions and isolation regions on the substrate, step (a) further including the step of:

(i) precleaning the silicon substrate prior to the double liner oxidation, thereby creating undercuts in the pad oxide to expose the trench corners for the subsequent oxidation processes.

3. The method of claim 2 wherein step (a) further includes the step of:

(i) removing approximately 100-300 angstroms of the pad oxide.

4. The method of claim 2 wherein step (b) further includes the steps of:

(i) performing a first liner oxidation process on the trenches in which a first layer of oxide is grown in the trenches;

(ii) removing the first layer of oxide from the trenches; and

(iii) performing a second liner oxidation process on the trenches after removal of the first layer of oxide from the trenches in which a second layer of oxide is grown in the trenches.

5. The method of claim 4 wherein prior to step (c), the method further includes the steps of:

depositing an isolation oxide over the substrate;

polishing the isolation oxide back so that the isolation oxide is approximately level with the masking material; and

removing the masking material.

6. The method of claim 5 further including the step of: performing a standard clean on the active regions of the substrate after removing the masking material.

7. The method of claim 4 wherein step (c) further includes the steps of:

(i) performing a first sacrificial oxidation process on the substrate in which a first layer of oxide is grown on the substrate;

(ii) removing the first layer of oxide from the trenches; and

(iii) performing a second sacrificial oxidation process on the substrate in which a second layer of oxide is grown on the substrate.

8. The method of claim 7 further including the steps of:

(d) continuing with the fabrication process, including patterning a layer of polysilicon over the substrate in the active regions, wherein due to the rounded trench corners, electron leakage between the polysilicon and the silicon substrate is substantially reduced.

Assignments (11)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2022
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES LLC
Reel/Frame 059721/0467 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036039/0406 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 22, 2007
From: SPANSION INC.
To: SPANSION LLC
Reel/Frame 019052/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2007
From: ADVANCED MICRO DEVICES, INC.
To: SPANSION INC.
Reel/Frame 019029/0976 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2002
From: KIM, UNSOON; SUN, YU; KINOSHITA, HIROYUKI; CHANG, KUO-TUNG; SACHAR, HARPREET K.; CHANG, MARK S.
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 013422/0047 →