Junction temperatures measurements in semiconductor chip package technology
View Patent ↗A need exists in the art for a method of generating junction temperatures for multiple-chip packages that takes into account the non-linearity of thermal systems, improves accuracy, and allows more than one multiple-chip package to be measured without again determining the power distribution ratio of each device. To meet this need, the invention includes a method of generating junction temperatures in a multiple-chip package by heating a single chip in the multiple-chip package, measuring the change in temperature of each chip in the multiple-chip package, storing the measured temperature change of each chip, and repeating the heating, measuring, and storing steps for each chip in the multiple-chip package. The invention generates the junction temperatures of each chip in the multiple-chip package when each chip is operating simultaneously based on the stored measured temperature changes and accounting for a non-linearity in a thermal system of the multiple-chip package based on power dissipation ratios of each chip.
1. A method of generating junction temperatures in a multiple-chip package comprising the steps of:
heating a single chip in the multiple-chip package;
measuring the change in temperature of each chip in the multiple-chip package;
storing the measured temperature change of each chip;
repeating the heating, measuring, and storing steps for each chip in the multiple-chip package; and
generating the junction temperatures of each chip in the multiple-chip package when each chip is operating simultaneously based on the stored measured temperature changes and accounting for a non-linearity in a thermal system of the multiple-chip package based on power dissipation ratios of each chip.
2. The method of claim 1 , wherein the heating step further comprises passing a current through the single chip.
3. The method of claim 1 , wherein the measuring step further comprises measuring a temperature sensitive parameter of each chip.
4. The method of claim 1 , wherein the measuring step further comprises passing a sensing current through each chip and measuring the voltage.
5. The method of claim 4 , wherein the measured voltage is converted into a temperature measurement.
6. The method of claim 1 , wherein the generating step further comprises calculating the junction temperature of each chip in the multiple-chip package when each chip is operating simultaneously by using an algorithm.
7. The method of claim 6 , wherein the generating step further comprises calculating the junction temperature of each chip in the multiple-chip package when each chip is operating simultaneously by compiling single-source temperatures from the stored measured temperatures.
8. The method of claim 7 , wherein the single-source temperatures further comprise a combination of multiple individual temperature rises of a single chip occurring when each chip is separately powered to give off heat during the heating, measuring, and repeating steps.
9. The method of claim 8 , wherein the single-source temperatures further comprise multiplying each temperature rise of a single chip by the power dissipation ratio of the chip which is separately powered to give off heat.
10. The method of claim 9 , wherein the single-source temperatures are entered into the algorithm and the junction temperature of each chip in the multiple-chip package when each chip is simultaneously operating is extracted.
11. A method of analyzing the dependence of junction temperatures in a multiple-chip package on power distribution ratios from a test-mode comprising the steps of:
heating a single chip in the multiple-chip package;
measuring the change in temperature of each chip in the multiple-chip package;
storing the measured temperature change of each chip;
repeating the heating, measuring, and storing steps for each chip in the multiple-chip package;
generating the junction temperatures of each chip in the multiple-chip package from the stored measured temperature changes and accounting for a non-linearity in a thermal system of the multiple-chip package based on a first power dissipation ratio of each chip; and
generating the junction temperatures of each chip in the multiple-chip package from the stored measured temperature changes and accounting for a non-linearity in a thermal system of the multiple-chip package based on a second power dissipation ratio of each chip.