IP Library Granted Patent US 7,200,164
Granted Patent B2
US 7,200,164 · App. 10/289,749 · Granted Apr 3, 2007

Packet-based multiplication-free CCK demodulator with a fast multipath interference cipher

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Quick Facts
Patent No.
US 7,200,164
App. No.
10/289,749
Granted
Apr 3, 2007
Kind
B2
Abstract

A complementary code keying (CCK) demodulator used in a RAKE receiver receiving CCK symbols in a multipath environment computes multipath interferences (MPIs) required for canceling intra-codeword chip interference (ICI). The algorithmic structure jointly computes the ICI of a plurality of possible codewords. The algorithmic structure is similar to the optimal architecture required for CCK correlation computations. The similarity between these two structures allows for the use of the same hardware at different times to compute MPIs and to compute the CCK correlation of a plurality of possible codewords.

Claims (16)

1. A complementary code keying (CCK) demodulator used in a RAKE receiver receiving CCK symbols in a multipath environment, the CCK demodulator comprising:

multipath interference estimation means, using feedback and feed-forward tap weights as inputs to a modified Fast Walsh Transform (FWT) based CCK correlator for jointly calculating a plurality of post-correlation intra-codeword chip interference (ICI) bias during a preamble period;

decoding means, using the same modified FWT based CCK correlator during a CCK data period for computing the correlation between the received CCK symbol and all possible CCK codewords, and then finding an index of a CCK codeword having the maximum correlation between the received CCK symbol and all possible CCK codewords, with the post-correlation ICI bias due to the received present (“to-be-decoded”) CCK symbol removed; and

wherein the modified FWT based CCK correlator, using a Fast Multipath/Walsh Transform (FMWT) block as its basic building blocks, forms an optimum CCK demodulator in the absence of multipath propagation.

2. The CCK demodulator of claim 1 , further comprising:

channel estimation means for estimating a channel impulse response (CIR) and generating the feedback and feed forward tap weights during the preamble period; and

a channel matching filter, with the tap weights based on the estimated CIR, for optimally collecting a multipath energy for the received CCK symbols before the CCK demodulator during the CCK data period.

3. The CCK demodulator of claim 1 , wherein the decoding means comprises:

mapping means coupled to receive the output of the multipath interference estimation mean for permuting and storing the output of the multipath interference estimation mean.

4. The CCK demodulator of claim 3 , wherein the mapping mean comprises:

means to further reduce the computating number of post-correlation ICI bias (from 256 to 32 or 16), or equivalently, the number of active basic FMWT blocks needed for obtaining the post-correlation ICI biases for all the CCK codewords.

5. A method for computing the post-correlation Intra-Codeword Chip Interference (ICI) bias of a received symbol, the method comprising:

utilizing the auto-correlation properties of the codewords with multiple symbols in a reduced-complexity demodulator;

wherein the reduced-complexity demodulator, in the absence of multipath, contains a Fast Transform (Walsh, Hadamard, or Fourier) based correlator to operate in two modes at different times;

in a first mode the modified Fast Transform based correlator is a multipath interference cipher that receives feedback tap weights and feed-forward tap weights, and jointly calculates a plurality of post-correlation ICI bais; and

in a second mode the modified FWT based correlator is a correlator that receives chips of the received symbol and calculates the correlations between the received chips and a plurality of codewords of the received symbol.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 059666/0545 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: MICROCHIP TECHNOLOGY INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041675/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2015
From: MICROCHIP TECHNOLOGY (BARBADOS) II INCORPORATED
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 036631/0442 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2015
From: ISSC TECHNOLOGIES CORP.
To: MICROCHIP TECHNOLOGY (BARBADOS) II INCORPORATED
Reel/Frame 036554/0001 →
MERGER Recorded Sep 4, 2015
From: ISSC TECHNOLOGIES CORP.
To: MICROCHIP TECHNOLOGY (BARBADOS) II INCORPORATED
Reel/Frame 036554/0052 →
CHANGE OF NAME Recorded Jul 13, 2010
From: INTEGRATED SYSTEM SOLUTION CORP.
To: ISSC TECHNOLOGIES CORP.
Reel/Frame 024675/0495 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2006
From: WINBOND ELECTRONICS CORP.
To: INTEGRATED SYSTEM SOLUTION CORP.
Reel/Frame 017711/0367 →