Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics

1. A non-volatile memory cell comprising:

a magnetic tunnel junction (MTJ) storage element having at least a first ferromagnetic layer, an insulating layer and a second ferromagnetic layer; and

an asymmetric tunnel device connected in series with the MTJ storage element, the asymmetric tunnel device being asymmetric by conducting electrons in a forward biased direction at a significantly higher rate than in a reversed biased direction.

2. The non-volatile memory cell of claim 1 wherein the asymmetric tunnel device is a metal-insulator-metal (MIM) device.

3. The non-volatile memory cell of claim 1 wherein the asymmetric tunnel device is a metal-insulator-metal-insulator-metal (MIMIM) device.

4. The non-volatile memory cell of claim 1 wherein the asymmetric tunnel device is a metal-insulator-insulator-metal (MIIM) device.

5. The non-volatile memory cell of claim 1 wherein the asymmetric tunnel device further comprises a first layer separated from a second layer by an insulator, the first layer comprising a first material having a first work function and the second layer comprising a second material having a second work function, the first work function differing from a second work function in a range from substantially 0.20 eV to 0.6 eV, and a barrier height between each of the first material and the second material to the insulator is in a range from substantially 0.0 eV to 0.6 eV.

6. The non-volatile memory cell of claim 1 wherein forward biased tunneling conduction of the asymmetric tunnel device is at least ten times greater than reverse biased tunneling conduction of the asymmetric tunnel device when the non-volatile memory cell is biased at substantially plus and minus one-half volt, respectively.

7. The non-volatile memory cell of claim 1 wherein the first ferromagnetic layer, the insulating layer and the second ferromagnetic layer of the MTJ storage element are stacked and the asymmetric tunnel device is stacked with the MTJ storage element.

8. The non-volatile memory cell of claim 7 wherein the first ferromagnetic layer, the insulating layer and the second ferromagnetic layer of the MTJ storage element are stacked above the asymmetric tunnel device.

9. The non-volatile memory cell of claim 1 wherein the asymmetric tunnel device comprises a first layer of tantalum, a second layer of titanium oxide and a third layer of titanium nitride.

10. The non-volatile memory cell of claim 1 wherein the asymmetric tunnel device comprises a first layer of tantalum, a second layer comprising at least one of strontium titanate, tantalum pentoxide and strontium bismuth tantalate (SrBi 2 Ta 2 O 9 ) and a third layer of titanium nitride.

11. A non-volatile memory array comprising:

a plurality of bit lines;

a plurality of word lines;

an array of memory cells, each of the memory cells being formed at an intersection of a predetermined one of the plurality of bit lines and the plurality of word lines;

a row decoder and drivers coupled to each of the plurality of word lines for decoding a memory address and selecting a predetermined word line in response;

a column decoder coupled to each of the plurality of bit lines for decoding the memory address and selecting a predetermined bit line in response;

each of the memory cells comprising:

a magnetic tunnel junction (MTJ) storage element having at least a first ferromagnetic layer, an insulating layer and a second ferromagnetic layer; and

an asymmetric tunnel device formed in a stack with the MTJ storage element, the asymmetric tunnel device being asymmetric by conducting electrons in a forward biased direction at a significantly higher rate than in a reversed biased direction.

12. The non-volatile memory array of claim 11 wherein the asymmetric tunnel device comprises a first layer separated from a second layer by an insulator, the first layer comprising a first material having a first work function and the second layer comprising a second material having a second work function, the first work function differing from a second work function in a range from substantially 0.20 eV to 0.6 eV, and a barrier height between each of the first material and the second material to the insulator being in a range from substantially 0.0 eV to 0.6 eV.

13. The non-volatile memory array of claim 12 wherein the first layer comprises tantalum (Ta), the second layer comprises titanium nitride (TiN) and the insulator comprises titanium oxide (TiO 2 ).

14. The non-volatile memory array of claim 11 wherein the asymmetric tunnel device comprises one of a metal-insulator-metal (MIM) device, a metal-insulator-metal-insulator-metal (MIMIM) device and a metal-insulator-insulator-metal (MIIM) device.

15. The non-volatile memory array of claim 11 , wherein the memory cell has a first terminal coupled to the MTJ on a first end of the stack and a second terminal on a second end of the stack, and wherein the asymmetric tunnel device comprises:

a first metal layer adjacent to the MTJ and in the stack;

a second metal layer in the stack and coupled to the second terminal; and

a first insulator layer in the stack between the first and second metal layer.

16. The non-volatile memory of claim 15 , wherein the asymmetric tunnel device further comprises a second insulator layer in the stack between the first insulator layer and the second metal layer.

17. The non-volatile memory of claim 16 , wherein the asymmetric tunnel device further comprises a third metal layer in the stack between the first and second insulator layers.

18. The non-volatile memory of claim 17 , wherein the first and second insulators have different work functions.