Panel stacking of BGA devices to form three-dimensional modules
View Patent ↗A chip stack comprising at least one base layer including a base substrate having a first conductive pattern disposed thereon. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon which is electrically connected to the first conductive pattern of the base layer. Also included in the chip stack are at least two integrated circuit chip packages. The integrated circuit chip packages may each be electrically connected to the first conductive pattern of the base layer such that one of the integrated circuit chip packages is at least partially circumvented by the interconnect frame. Alternatively, one of the integrated circuit chip packages may be electrically connected to the first conductive pattern, with the remaining integrated circuit chip package being attached to the base substrate and at least partially circumvented by the interconnect frame such that the circumvented integrated circuit chip package and the second conductive pattern of the interconnect frame collectively define a composite footprint for the chip stack. A transposer layer may be included as a portion of each chip stack, with the transposer layer including a third conductive pattern specifically configured to provide a CSP-TSOP interface.
1. A method of assembling a chip stack, comprising the steps of:
a) electrically connecting an integrated circuit chip package to a first conductive pattern of a base layer;
b) electrically connecting a second conductive pattern of an interconnect frame to the first conductive pattern;
c) electrically connecting another integrated circuit chip package to a third conductive pattern of a transposer layer; and
d) electrically connecting the second conductive pattern of the interconnect frame to the third conductive pattern of the transposer layer such that one of the integrated circuit chip packages is at least partially circumvented by the interconnect frame.
2. A method of assembling a chip stack, comprising the steps of:
a) electrically connecting an integrated circuit chip package to a first conductive pattern of a base layer;
b) attaching a second integrated circuit chip packages to the base layer; and
c) electrically connecting a second conductive pattern of an interconnect frame to the first conductive pattern such that the interconnect frame at least partially circumvents the second integrated circuit chip package.
3. The method of claim 2 wherein step (b) is accomplished through the use of an adhesive.
4. The method of claim 2 wherein step (c) comprises orienting the interconnect frame such that the second integrated circuit chip package and the second conductive pattern of the interconnect frame collectively define a composite footprint electrically connectable to another component.
5. A method of assembling a chip stack, comprising the steps of:
a) electrically connecting an integrated circuit chip package to a first conductive pattern of a base layer;
b) electrically connecting another integrated circuit chip package to the first conductive pattern of the base layer; and
c) electrically connecting a second conductive pattern of an interconnect frame to the first conductive pattern such that the interconnect frame at least partially circumvents one of the integrated circuit chip packages.
6. The method of claim 5 wherein:
step (a) comprises positioning one of the integrated circuit chip packages upon a top surface of the base layer;
step (b) comprises positioning one of the integrated circuit chip packages upon a bottom surface of the base layer; and
step (c) comprises electrically connecting the second conductive pattern of the interconnect frame to the first conductive pattern of the base layer such that the interconnect frame at least partially circumvents the integrated circuit chip package positioned upon the bottom surface of the base layer.