Memory cell arrangement and method of fabricating it
View Patent ↗Memory cell arrangement having a memory cell array which has at least one layer of magnetoresistive memory components ( 11 ) which are each connected to first contact-making lines ( 10 ), the first contact-making lines ( 10 ) lying within a first dielectric layer ( 6 ), and are each connected to second contact-making lines ( 20; 29; 35 ), the second contact-making lines ( 20; 29; 35 ) lying within a second dielectric layer ( 17; 27; 32 ).
1. A memory cell arrangement comprising:
a memory cell array having at least one layer of magnetoresistive memory components, each of which has at least two ferromagnetic layers,
first and second dielectric layers,
copper first contact-making lines lying within the first dielectric layer, the first contact-making lines being connected to a first of the at least two ferromagnetic layers,
copper second contact-making lines lying within the second dielectric layer, the second contact-making lines being connected to a second of the at least two ferromagnetic layers, and
a silicon nitride diffusion barrier layer between the first contact-making lines and the second dielectric layer, the diffusion barrier layer being in direct contact with the magnetoresistive memory components and being configured to minimize memory drift
by suppressing diffusion of copper out of the first contact-making lines into the second dielectric layer and into the magnetoresistive memory components, and
by suppressing interdiffusion between the ferromagnetic layers and the first contact-making lines.
2. The memory cell arrangement according to claim 1 , wherein the magnetoresistive memory components comprise TMR memory components, each of which comprises
two ferromagnetic layers, and
an insulating nonmagnetic layer between the two ferromagnetic layers.
3. The memory cell arrangement according to claim 1 , wherein the magnetoresistive memory components comprise GMR memory components, each of which comprises
two ferromagnetic layers, and
a conductive nonmagnetic layer between the two ferromagnetic layers.
4. The memory cell arrangement according to claim 1 , wherein the magnetoresistive memory components are each connected to the contact-making lines via contact-making diffusion barrier layers.
5. The memory cell arrangement according to claim 4 , wherein the contact-making diffusion barrier layers comprise tantalum.
6. The memory cell arrangement according to claim 1 , further comprising:
a third dielectric layer disposed on a semiconductor substrate,
a second diffusion barrier layer and
a liner,
the second diffusion barrier layer and the liner being disposed to separate the third dielectric layer from the first contact making lines.
7. The memory cell arrangement according to claim 1 wherein the first and second dielectric layers comprise silicon dioxide.
8. A method for fabricating the memory cell arrangement according to claim 1 , the method comprising:
(a) depositing and patterning the first contact-making lines in the first dielectric layer;
(b) depositing and patterning the magnetoresistive memory components in the memory cell array;
(c) depositing and patterning the diffusion barrier layer such that the diffusion barrier layer is in direct contact with the magnetoresistive memory components;
(d) making self-aligned contacts with the semiconductor components by etching back a hard mask that defines the patterning of the magnetoresistive memory components,
(e) depositing and patterning the second contact-making lines in the second dielectric layer.