Semiconductor device and its manufacturing method
View Patent ↗In a contact structure having a large aspect ratio in a LSI device incorporating DRAM cells and logics, for the purpose of preventing over-etching of a device isolation insulating film and an impurity diffusion layer and thereby minimizing junction leakage, a first etching stopper layer covering a peripheral MOS transistor and a second etching stopper layer overlying a capacitor section of a DRAM memory cell are formed. An impurity diffusion layer of the peripheral MOS transistor is connected to a metal wiring layer formed in an upper level of the capacitor section by an electrode layer extending through the first and second etching stopper layers. At least one of such impurity diffusion layers is connected to the electrode layer at its boundary with the device isolation insulating film, and depth of the bottom of the electrode layer formed on the device isolation insulating film from the surface of the impurity diffusion layer is shorter than the junction depth of the impurity diffusion layer.
1. A semiconductor device including a DRAM memory cell and a peripheral MOS transistor, comprising:
a first etching stopper layer covering at least one of an impurity diffusion layer and a gate electrode of said peripheral MOS transistor;
a second etching stopper layer formed above at least a portion of said first etching stopper layer and separated from said first etching stopper layer by a distance;
at least one of said impurity diffusion layer and said gate electrode of said peripheral MOS transistor being connected to a metal wiring layer formed in an upper level of a capacitor section of said DRAM memory cell by an electrode layer extending through said first etching stopper layer and said second etching stopper layer;
said impurity diffusion layer being connected to said electrode layer at a boundary between said impurity diffusion layer and a device isolation insulating film;
wherein a bottom portion of said electrode layer formed on said device isolation insulating film measured from a surface of said impurity diffusion layer has a length shorter than one of a junction depth of said impurity diffusion layer and a thickness of said first etching stopper layer.
2. A semiconductor device including a DRAM memory cell and a peripheral MOS transistor, comprising:
a first etching stopper layer covering at least one of an impurity diffusion region and a gate electrode of said peripheral MOS transistor region;
a second etching stopper layer formed above at least a portion of said first etching stopper layer and separated from said first etching stopper layer by a distance;
at least one of said impurity diffusion layer and said gate electrode of said peripheral MOS transistor being connected to a metal wiring layer formed in an upper level of a capacitor section of said DRAM memory cell by an electrode layer extending through said first etching stopper layer and said second etching stopper layer;
said impurity diffusion layer being connected to said electrode layer at a boundary between said impurity diffusion layer and a device isolation insulating film;
wherein a bottom portion of said electrode layer formed on said device isolation insulating film measured from a surface of said impurity diffusion layer has a length shorter than a junction depth of said impurity diffusion layer.
3. A semiconductor device including a DRAM memory cell and a peripheral MOS transistor, comprising:
a first etching stopper layer covering at least one of an impurity diffusion region and a gate electrode of said peripheral MOS transistor region;
a second etching stopper layer formed above at least a portion of said first etching stopper layer and separated from said first etching stopper layer by a distance;
at least one of said impurity diffusion layer and said gate electrode of said peripheral MOS transistor being connected to a metal wiring layer formed in an upper level of a capacitor section of said DRAM memory cell by an electrode layer extending through said first etching stopper layer and said second etching stopper;
said impurity diffusion layer being connected to said electrode layer at a boundary between said impurity diffusion layer and a device isolation insulating film;
wherein a bottom portion of said electrode layer formed on said device isolation insulating film measured from a surface of said impurity diffusion layer has a length shorter than a thickness of said first etching stopper layer.
4. A semiconductor device including a DRAM memory cell and a peripheral MOS transistor, comprising:
a first etching stopper layer covering at least one of an impurity diffusion region and a gate electrode of said peripheral MOS transistor region;
a second etching stopper layer formed above at least a portion of said first etching stopper layer and separated from said first etching stopper layer by a distance; and
an electrode layer connected to a bit line of said DRAM memory cell through said second etching stopper layer;
wherein a bottom portion of said electrode layer measured from a surface of said device isolation insulating film has a length shorter than a thickness of said device isolation insulating film.
5. A semiconductor device including a DRAM memory cell and a peripheral MOS transistor, comprising:
a first etching stopper layer covering at least one of an impurity diffusion region and a gate electrode of said peripheral MOS transistor region;
a second etching stopper layer formed above at least a portion of said first etching stopper layer and separated from said first etching stopper layer by a distance; and
an electrode layer connected to a bit line of said DRAM memory cell through said second etching stopper layer;
wherein a bottom portion of an electrode layer measured from a surface of said impurity diffusion region has a length shorter than a junction depth of said impurity diffusion region.
6. A semiconductor device comprising:
a device isolation insulating film including a unitary impurity diffusion layer;
a peripheral MOS transistor having a gate electrode mounted in communication with the impurity diffusion layer;
a first etching stopper layer covering the gate electrode of the peripheral MOS transistor;
a DRAM memory cell having a capacitor section;
a second etching stopper layer formed on the capacitor section of said DRAM memory cell; and
an electrode layer connecting said unitary impurity diffusion layer and the gate electrode to a metal wiring layer formed in the capacitor section of the DRAM memory cell, said electrode layer extending through said first etching stopper layer and said second etching stopper layer, and adjoining said unitary impurity diffusion layer at a boundary between said unitary impurity diffusion layer and the device isolation insulating film;
wherein a bottom portion of said electrode layer has a length shorter than at least one of a junction depth of said unitary impurity diffusion layer and a thickness of said first etching stopper layer.
7. A semiconductor device as set forth in claim 6 wherein the bottom portion of said electrode layer has a length shorter than the junction depth of said impurity diffusion layer.
8. A semiconductor device as set forth in claim 7 wherein the bottom portion of said electrode layer has a length shorter than a thickness of said device isolation insulating film.
9. A semiconductor device as set forth in claim 7 wherein the bottom portion of said electrode layer has a length shorter than the thickness of said first etching stopper layer.
10. A semiconductor device as set forth in claim 7 wherein the bottom portion of said electrode layer has a length shorter than a thickness of said device isolation insulating film.
11. A semiconductor device as set forth in claim 6 wherein the bottom portion of said electrode layer has a length shorter than the thickness of said first etching stopper layer.
12. A semiconductor device as set forth in claim 6 further comprising a plurality of insulating films between said first etching stopper layer and said second etching stopper layer.
13. A semiconductor device as set forth in claim 6 further comprising a plurality of insulating films formed on said second etching stopper layer.
14. A semiconductor device including a DRAM memory cell and a peripheral MOS transistor, said device comprising:
a device isolation insulating film including a unitary impurity diffusion layer;
a first etching stopper layer covering a gate electrode of the peripheral MOS transistor;
a second etching stopper layer formed in a capacitor section of said DRAM memory cell; and
an electrode connecting said impurity diffusion layer and the gate electrode to a metal wiring layer in the capacitor section of the DRAM memory cell, said electrode extending through said first etching stopper layer and said second stopper layer, and adjoining said impurity diffusion layer and the device isolation insulating film;
wherein a bottom portion of said electrode has a length shorter than at least one of a junction depth of said impurity diffusion layer and a thickness of said first etching stopper layer.
15. A semiconductor device comprising:
a device isolation insulating film including a unitary impurity diffusion layer;
a peripheral MOS transistor having a gate electrode mounted in communication with said impurity diffusion layer;
a first etching stopper layer covering at least the gate electrode of the peripheral MOS transistor;
a DRAM memory cell having a capacitor section;
a second etching stopper layer formed on the capacitor section of said DRAM memory cell; and
an electrode layer connecting said unitary impurity diffusion layer and the gate electrode to a metal wiring layer formed in the capacitor section of the DRAM memory cell, said electrode layer extending through said first etching stopper layer and said second etching stopper layer, and adjoining said impurity diffusion layer at a boundary between said unitary impurity diffusion layer and the device isolation insulating film;
wherein a bottom portion of said electrode layer has a length shorter than at least one of a junction depth of said unitary impurity diffusion layer and a thickness of said first etching stopper layer; and
wherein the distance between said first etching stopper layer and said second stopper layer is substantially uniform above at least a portion of said impurity diffusion layers.
16. A semiconductor device comprising:
a device isolation insulating film including a unitary impurity diffusion layer;
a peripheral MOS transistor having a gate electrode mounted in communication with said impurity diffusion layer;
a first etching stopper layer covering at least the gate electrode of the peripheral MOS transistor;
a DRAM memory cell having a capacitor section;
a second etching stopper layer formed on the capacitor section of said DRAM memory cell; and
an electrode layer connecting said unitary impurity diffusion layer and the gate electrode to a metal wiring layer formed in the capacitor section of the DRAM memory cell, said electrode layer extending through said first etching stopper layer and said second etching stopper layer, and adjoining said impurity diffusion layer at a boundary between the unitary impurity diffusion layer and the device isolation insulating film;
wherein a bottom portion of said electrode layer has a length shorter than at least one of a junction depth of said unitary impurity diffusion layer and a thickness of said first etching stopper layer; and
wherein the distance between said first etching stopper layer and said second stopper layer is substantially uniform above at least a portion of the gate electrode.