Granted Patent B2

US 7,007,134 · App. 10/355,177 · Granted Feb 28, 2006

Abstract

Claims (22)

1. A microcomputer equipped with a cache memory, comprising:

a process switch control circuit that includes a first register, and stores cache usage information specifying cache memory usage rules for execution of a next process in the first register every time processes to be executed are switched; and

a cache control circuit that includes a second register, stores the cache usage information in the second register after the cache usage information has been stored in the first register, and performs data input and output on the cache memory in accordance with the cache memory usage rules specified by the cache usage information stored in the second register.

2. The microcomputer according to claim 1 , further comprising a cache usage information storing register that receives and holds the cache usage information of each process to be executed,

wherein the process switch control circuit obtains the cache usage information of a next process to be executed from the cache usage information storing register, and stores the obtained cache usage information in the first register.

3. The microcomputer according to claim 1 , wherein the cache usage information specifies whether the cache memory is to be used in execution of each process.

4. The microcomputer according to claim 1 , wherein the cache usage information is entry lock information that specifies whether new data are allowed to be stored in the cache memory in a case where a process is being executed using the cache memory.

5. The microcomputer according to claim 1 , wherein the process switch control circuit compares a priority level of a process being currently executed with a priority level of the next process to be executed, and, if the priority level of the next process to be executed is higher than the priority level of the process being currently executed, stores the cache usage information in the first register.

6. The microcomputer according to claim 1 , further comprising:

a memory into or out of which the value stored in the first register is inputted or outputted every time the process switch control circuit switches processes to be executed; and

a stack pointer that holds the address of the memory, and performs a subtraction or an addition on the address when the value of the first register is inputted or outputted into or out of the memory.

7. The microcomputer according to claim 1 , wherein the first register is a part of a program status register.

8. A method of controlling a cache memory of a microcomputer, comprising the steps of:

storing cache usage information specifying cache memory usage rules for execution of next process in a first register, every time processes to be executed are switched;

storing the cache usage information in a second register, after the cache usage information has been stored in the first register; and

performing data input and output on the cache memory in accordance with the cache memory usage rules specified by the cache usage information stored in the second register.

9. A method of controlling computer memory comprising:

storing memory usage data specifying memory usage rules for execution of a next operation in a first register;

storing the memory usage data in a second register, after the memory usage data has been stored in the first register; and

performing input and output in the computer memory in accordance with the memory usage rules specified by the memory usage data stored in the second register.

10. The method of controlling computer memory according to claim 9 , wherein memory usage data specifying memory usage rules for execution of a next operation are stored in the first register every time operations to be executed are switched.

11. The method of controlling computer memory according to claim 10 , wherein the execution of the next operation is in synchronization with a clock.

Assignments (8)