Fault simulator for verifying reliability of test pattern
View Patent ↗A fault simulator includes a circuit identifying section that selects, as fault generation points, circuit components subjected to a simulation from timing simulation results obtained by a static timing simulation of an LSI circuit; a fault value computing section that generates delay faults corresponding to the fault generation points using information about delay time and timing of signal transmission in the timing simulation result; and a fault simulating section that performs, by using a test pattern of the simulation, a logic simulation of a normal circuit of the LSI circuit and that of a faulty circuit where the delay faults are inserted into the fault generation points, and verifies detectability of the delay faults by the test pattern from the compared results of both the logic simulations. The fault simulator can reduce the time of the fault simulation.
1. A fault simulator comprising:
a fault position selection section that receives simulation result information obtained by a static timing simulation about delay time and timing of signal transmission in a semiconductor integrated circuit, and selects circuit components subjected to the simulation from the simulation result information as fault generation points;
a delay fault generator for generating delay faults corresponding to the fault generation points using the information about the delay time and timing of the signal transmission in the simulation result information; and
a fault simulating section that carries out, by using a test pattern to be verified, a logic simulation of a normal circuit of the semiconductor integrated circuit and a logic simulation of a faulty circuit in which the delay faults are inserted into the fault generation points, and verifies detectability of the delay faults by the test pattern from compared results of both the logic simulations,
wherein said fault position selection section selects, as the fault generation points, the circuit components with temporal margin less than a predetermined threshold value, the temporal margin being associated with timing conditions concerning the signal transmission, which are set in advance in the semiconductor integrated circuit.
2. The fault simulator according to claim 1 , wherein said fault position selection section selects, as the fault generation points, the circuit components specified in advance among the circuit components simulated in the simulation result information.