IP Library Granted Patent US 6,933,617
Granted Patent B2
US 6,933,617 · App. 10/373,413 · Granted Aug 23, 2005

Wafer interposer assembly

Assignee: Eaglestone Partners I, LLC
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,933,617
App. No.
10/373,413
Granted
Aug 23, 2005
Kind
B2
Abstract

A wafer interposer assembly and a system for building the same are disclosed. The wafer interposer assembly includes a semiconductor wafer ( 10 ) having a die ( 11 ) and a redistribution layer pad ( 13 ) electrically connected to the die ( 11 ). An epoxy layer ( 20 ) is deposited on the surface of the redistribution layer pad ( 13 ) and the die ( 11 ). An interposer pad ( 50 ) is positioned in an opening ( 40 ) in the epoxy layer ( 20 ) in electrical contact with the redistribution layer pad ( 13 ).

Claims (42)

1. A wafer interposer assembly comprising:

a semiconductor wafer having a die;

a redistribution layer (RDL) pad electrically connected to the die;

an epoxy layer deposited on the surface of the redistribution layer pad and, the die, the epoxy layer having an opening therethrough about the redistribution layer pad, and

an interposer pad positioned in the opening in electrical contact with the redistribution layer pad.

2. The wafer interposer assembly as recited in claim 1 , wherein the semiconductor wafer includes a plurality of die.

3. The wafer interposer assembly as recited in claim 1 , wherein the redistribution layer pad comprises a material reflective to laser frequencies.

4. The wafer interposer assembly as recited in claim 1 , wherein the redistribution layer pad comprises a material compatible with solder.

5. The wafer interposer assembly as recited in claim 1 , wherein the redistribution layer pad comprises a material compatible with conductive polymer.

6. The wafer interposer assembly as recited in claim 1 , wherein the epoxy layer is disposed on the surface by a deposition process selected from the group consisting of spraying, rolling and vapor deposition.

7. The wafer interposer assembly as recited in claim 1 , wherein the epoxy layer comprises a nonconductive material having a coefficient of thermal expansion similar to the wafer.

8. The wafer interposer assembly as recited in claim 1 , wherein the height of the epoxy layer is at least the length of the redistribution layer pad.

9. The wafer interposer assembly as recited in claim 1 , wherein the epoxy layer is cured.

10. The wafer interposer assembly as recited in claim 1 , wherein the epoxy layer is cured by a processes selected from the group consisting of heat processes and chemical processes.

11. The wafer interposer assembly as recited in claim 1 , wherein the epoxy layer is trimmed to achieve a flat surface and controlled height.

12. The wafer interposer assembly as recited in claim 1 , wherein the epoxy layer is trimmed by a laser process to achieve a flat surface and controlled height.

13. The wafer interposer assembly as recited in claim 1 , wherein the interposer pad comprises a conductive material.

14. The wafer interposer assembly as recited in claim 1 , wherein the opening is formed by a laser process.

15. The wafer interposer assembly as recited in claim 1 , further comprising an epoxy coat disposed on a backside of the wafer.

16. A wafer interposer assembly comprising:

a semiconductor wafer having a plurality of die;

a plurality of redistribution layer pads electrically connected to each die, the redistribution layer pads including a material reflective to laser frequencies;

an epoxy layer deposited on the surface of the redistribution layer pads and the dies, the epoxy layer having a plurality of openings therethrough corresponding to the redistribution layer pads, the epoxy layer having a flat surface that is trimmed to a height of at least the length of the redistribution layer pads; and

a plurality of interposer pads positioned in the openings in electrical contact with the redistribution layer pads.

17. The wafer interposer assembly as recited in claim 16 , wherein the epoxy layer is trimmed by a laser process to achieve a flat surface and controlled height.

18. The wafer interposer assembly as recited in claim 16 , wherein the openings are formed by a laser process.

19. A wafer interposer assembly comprising:

a semiconductor wafer having a die disposed therein having a surface having a peripheral region and an inboard region;

a plurality of die pads disposed on the peripheral region of the die;

a plurality of redistribution layer pads disposed on the inboard region of the die, at least one redistribution layer pad being electrically connected to at least one die pad via a connector;

an epoxy layer deposited on the surface of the redistribution layer pad and the die, the epoxy layer having an opening therethrough about the redistribution layer pad; and

an interposer pad positioned in the opening in electrical contact with the redistribution layer pad.

20. The water interposer assembly am recited in claim 19 , wherein the semiconductor wafer includes a plurality of die.

21. The wafer interposer assembly as recited in claim 19 , wherein the redistribution layer pads comprise a material reflective to laser frequencies.

22. The wafer interposer assembly as recited in claim 19 , wherein the redistribution layer pads comprise a material compatible with solder.

23. The wafer interposer assembly as recited in claim 19 , wherein the redistribution layer pads comprise a material compatible with conductive polymer.

24. The wafer interposer assembly as recited in claim 19 , wherein the epoxy layer is disposed on the surface by a deposition process selected from the group consisting of spraying, rolling and vapor deposition.

25. The wafer interposer assembly as recited in claim 19 , wherein the epoxy layer comprises nonconductive material having a coefficient of thermal expansion similar to the wafer.

26. The wafer interposer assembly as recited in claim 19 , wherein the height of the epoxy layer is at least the length of a redistribution layer pad.

27. The wafer interposer assembly as recited in claim 19 , wherein the epoxy layer is cured.

28. The wafer interposer assembly as recited in claim 19 , wherein the epoxy layer is cured by a processes selected from the group consisting of heat processes and chemical processes.

29. The wafer interposer assembly as recited in claim 19 , wherein the epoxy layer is trimmed to achieve a flat surface and controlled height.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2023
From: INTELLECTUAL VENTURES ASSETS 191 LLC
To: MIND FUSION, LLC
Reel/Frame 064270/0685 →
SECURITY INTEREST Recorded Mar 24, 2023
From: MIND FUSION, LLC
To: INTELLECTUAL VENTURES ASSETS 191 LLC; INTELLECTUAL VENTURES ASSETS 186 LLC
Reel/Frame 063295/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2023
From: TRANSPACIFIC MULTICAST, LLC
To: INTELLECTUAL VENTURES ASSETS 191 LLC
Reel/Frame 062666/0758 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2008
From: EAGLESTONE INVESTMENT PARTNERS I, L.P.
To: TRANSPACIFIC MULTICAST, LLC
Reel/Frame 021450/0271 →
SECURITY AGREEMENT Recorded Jun 13, 2005
From: MICRO-ASI, INC.
To: EAGLESTONE INVESTMENT PARTNERS I, L.P.
Reel/Frame 016127/0641 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2003
From: PIERCE, JOHN L.
To: MICRO-ASI, INC.
Reel/Frame 013818/0469 →
Continuity (2)
Division 0973822800 · Dec 15, 2000
Related Publication 20030148108A1 · Aug 7, 2003