IP Library Granted Patent US 6,960,529
Granted Patent B1
US 6,960,529 · App. 10/373,911 · Granted Nov 1, 2005

Methods for sidewall protection of metal interconnect for unlanded vias using physical vapor deposition

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Quick Facts
Patent No.
US 6,960,529
App. No.
10/373,911
Granted
Nov 1, 2005
Kind
B1
Abstract

Methods for protecting the sidewall of a metal interconnect component using Physical Vapor Deposition (PVD) processes and using a single barrier metal material. After forming the metal interconnect component, a single barrier metal is deposited on its sidewall using PVD. A subsequent anisotropic etching of the barrier metal removes the barrier metal from the horizontal surface except for some that still remains on the top surface of the metal interconnect layer. A dielectric layer is then formed over the metal interconnect component and the barrier metal. The unlanded via is etched through the dielectric layer to the metal interconnect component, and then filled with a second metal to thereby allow the metal interconnect component to electrically connect with one or more upper metal layers.

Claims (45)

1. A method for fabricating a multiple-layered semiconductor interconnect device in which one metal layer is connected to another metal layer using one or more vias having metal interconnect sidewall protection against unlanded vias, the protection provided using a single barrier metal or compound without requiring Chemical Vapor Deposition (CVD) processes, the method comprising the following:

an act of forming a metal interconnect component;

an act of depositing a single barrier metal or compound directly on at least a portion of the metal interconnect component including at least a portion of a sidewall of the metal interconnect component using a Physical Vapor Deposition (PVD) process;

an act of forming a dielectric layer over the metal interconnect component and the single barrier metal or compound layer such that the dielectric layer is in direct contact with the single barrier metal or compound;

an act of etching an unlanded via through the dielectric layer to the metal interconnect component so that the single barrier metal or compound that covers at least a portion of the sidewall of the metal interconnect component is exposed at the sidewall of the metal interconnect component; and

an act of filling the unlanded via with a second metal to thereby allow the metal interconnect component to electrically connect with one or more upper metal layers.

2. A method in accordance with claim 1 , further comprising the following after the act of etching and before the act of filling:

an act of depositing a barrier metal on sidewalls of the unlanded via using a PVD process.

3. A method in accordance with claim 1 , further comprising the following before the act of forming a dielectric layer:

an act of anisotropically etching the single barrier metal or compound.

4. A method in accordance with claim 1 , wherein the act of forming a metal interconnect component composed of a first metal comprises the following:

an act of forming the metal interconnect component at least partially out of Aluminum.

5. A method in accordance with claim 1 , wherein the single barrier metal or compound is a material selected from the group consisting of Titanium Nitride, Titanium, Tantalum, Tantalum Nitride, and alloys of Titanium Nitride, Titanium, Tantalum, and Tantalum Nitride.

6. A method in accordance with claim 5 , wherein the act of filling the unlanded via with a second metal to thereby allow the metal interconnect component to electrically connect with one or more upper metal layers comprises the following:

an act of filling the unlanded via with Tungsten or any alloy of Tungsten.

7. A method in accordance with claim 1 , wherein the act of filling the unlanded via with a second metal to thereby allow the metal interconnect component to electrically connect with one or more upper metal layers comprises the following:

an act of filling the unlanded via with Tungsten or any alloy of Tungsten.

8. A method in accordance with claim 1 , wherein the act of forming a metal interconnect component composed of a first metal comprises the following:

an act of forming the metal interconnect component out of Copper.

9. A method in accordance with claim 1 , wherein the act of depositing a single barrier metal or compound directly on at least a portion of the metal interconnect component including at least a portion of a sidewall of the metal interconnect component using a Physical Vapor Deposition (PVD) process comprises the following:

an act of sputtering the single barrier metal or compound on the at least a portion of the metal interconnect component.

10. A method in accordance with claim 1 , wherein the act of depositing a single barrier metal or compound directly on at least a portion of the metal interconnect component including at least a portion of a sidewall of the metal interconnect component using a Physical Vapor Deposition (PVD) process comprises the following:

an act of depositing the single barrier metal or compound to a maximum thickness of between one hundred and one thousand Angstroms.

11. A method in accordance with claim 1 , wherein the act of forming a metal interconnect component composed of a first metal comprises the following:

an act of forming a Titanium Nitride bottom layer;

an act of forming an Aluminum metal layer on the Titanium Nitride bottom layer;

an act of forming a Titanium Nitride anti-reflective coating on the Aluminum metal layer; and

an act of patterning the Titanium Nitride bottom layer, the Aluminum metal layer, and the Titanium Nitride anti-reflective coating.

12. A method for fabricating a multiple-layered semiconductor interconnect device in which one metal layer is connected to another metal layer using one or more vias having metal interconnect sidewall protection against unlanded vias, the protection provided using a single barrier metal or compound without requiring Chemical Vapor Deposition (CVD) processes, the method comprising the following:

an act of forming a metal interconnect component composed of Aluminum

an act of depositing a single barrier metal or compound directly on at least a portion of the metal interconnect component including at least a portion of a sidewall of the metal interconnect component using a Physical Vapor Deposition (PVD) process, the single barrier metal or compound being a material selected from the group consisting of Titanium Nitride, Titanium, Tantalum, Tantalum Nitride, and alloys of Titanium Nitride, Titanium, Tantalum, and Tantalum Nitride;

an act of anisotropically etching the single barrier metal or compound;

after anisotropically etching the single barrier metal or compound, an act of forming a dielectric layer over the metal interconnect component and the single barrier metal or compound;

an act of forming a dielectric layer over the metal interconnect component and the single barrier metal layer or compound such that the dielectric layer is in direct contact with the single barrier metal or compound;

an act of etching an unlanded via through the dielectric layer to the metal interconnect component so that the single barrier metal or compound that covers at least a portion of the sidewall of the metal interconnect component is exposed at the sidewall of the metal interconnect component; and

an act of filling the unlanded via with Tungsten or an alloy of Tungsten to thereby allow the metal interconnect component to electrically connect with one or more upper metal layers.

13. A method in accordance with claim 12 , wherein the act of depositing a single barrier metal or compound directly on at least a portion of the metal interconnect component including at least a portion of a sidewall of the metal interconnect component using a Physical Vapor Deposition (PVD) process comprises the following:

an act of sputtering the single barrier metal or compound on the at least a portion of the metal interconnect component.

14. A method in accordance with claim 12 , wherein the act of depositing a single barrier metal or compound directly on at least a portion of the metal interconnect component including at least a portion of a sidewall of the metal interconnect component using a Physical Vapor Deposition (PVD) process comprises the following:

an act of depositing the single barrier metal or compound to a maximum thickness of between one hundred and one thousand Angstroms.

15. A method in accordance with claim 12 , wherein the act of forming a metal interconnect component composed of a first metal comprises the following:

an act of forming a Titanium Nitride bottom layer;

an act of forming an Aluminum metal layer on the Titanium Nitride bottom layer;

an act of forming a Titanium Nitride anti-reflective coating on the Aluminum metal layer; and

an act of patterning the Titanium Nitride bottom layer, the Aluminum metal layer, and the Titanium Nitride anti-reflective coating.

Assignments (13)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038631/0345 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A. (ON ITS BEHALF AND ON BEHALF OF ITS PREDECESSOR IN INTEREST, CHASE MANHATTAN BANK)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038632/0074 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
RELEASE OF SECURITY INTEREST Recorded Apr 5, 2016
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH (F/K/A CREDIT SUISSE FIRST BOSTON)
To: AMI SEMICONDUCTOR, INC.; AMI SPINCO, INC.
Reel/Frame 038355/0131 →
PURCHASE AGREEMENT DATED 28 FEBRUARY 2009 Recorded Sep 25, 2009
From: AMI SEMICONDUCTOR, INC.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 023282/0465 →
SECURITY AGREEMENT Recorded Jun 23, 2008
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; AMIS HOLDINGS, INC.; AMI SEMICONDUCTOR, INC.; AMIS FOREIGN HOLDINGS INC.; AMI ACQUISITION LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 021138/0070 →
PATENT RELEASE Recorded Mar 21, 2008
From: CREDIT SUISSE
To: AMI SEMICONDUCTOR, INC.
Reel/Frame 020679/0505 →
SECURITY INTEREST Recorded Jun 1, 2005
From: AMI SEMICONDUCTOR, INC.
To: CREDIT SUISSE (F/K/A CREDIT SUISEE FIRST BOSTON), AS COLLATERAL AGENT
Reel/Frame 016290/0206 →
SECURITY INTEREST Recorded Oct 15, 2003
From: AMI SEMICONDUCTOR, INC.
To: CREDIT SUISSE FIRST BOSTON, AS COLLATERAL AGENT
Reel/Frame 014546/0868 →
CORRECTIVE COVERSHEET TO CORRECT THE NAME OF ASSIGNEE THAT WAS PREVIOUSLY RECORDED ON REEL 013817, FRAME 0325. Recorded Aug 13, 2003
From: NELSON, MARK MICHAEL; WILLIAMS, BRETT N.; PRASAD, JAGDISH
To: AMI SEMICONDUCTOR, INC.
Reel/Frame 014385/0784 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2003
From: NELSON, MARK MICHAEL; WILLIAMS, BRETT N.; PRASAD, JAGDISH
To: AMI SEMICONDUCTORS, INC.
Reel/Frame 013817/0325 →