Deep power down switch for memory device
View Patent ↗A circuit to operate a semiconductor integrated circuit memory device having memory cells in a deep power down mode. The power down circuit includes a transistor switch connected between an external voltage source and the device memory cells and peripheral circuits, a generator for providing a control voltage of a first level different from the value of the external voltage, and a multiplexer that receives as one input the control voltage and as a second input the external voltage. The multiplexer has a selected output of one of the control voltage and external voltage that is applied to a control electrode of the transistor switch. When deep power down mode operation is required, the multiplexer responds to a power down control flag signal to apply the external voltage to the transistor control electrode to turn off the transistor and block application of the external voltage to the memory cells and peripheral circuits. In normal operation, no power down control flag signal is produced and the multiplexer applies the control voltage of a first level to the transistor switch control electrode to cause the transistor to conduct and apply the external voltage to the device memory cells and peripheral circuits for normal operation.
1. A power down circuit for a semiconductor integrated circuit memory device operating from an external voltage source and having memory cells and peripheral circuits comprising:
a transistor switch connected between the external voltage source and the memory cells and peripheral circuits;
a generator for providing a control voltage of a first level different from the external voltage;
a multiplexer receiving as one input said control voltage and as a second input the external voltage, said multiplexer having a selected output of one of said control voltage and said external voltage that is applied to a control electrode of said transistor switch;
wherein said multiplexer is responsive to a power down control signal to selectively apply the external voltage to said transistor control electrode to block application of the external voltage to the device memory cells and peripheral circuits, and responsive to the absence of the power down control signal to apply said control voltage to said transistor switch control electrode and operate said transistor to apply the external voltage to the device memory cells and peripheral circuits for normal operation of the memory device.
2. A power down circuit for a semiconductor device as claimed in claim 1 wherein said power down control signal is applied to said generator to turn off said generator during the time of the application of said power down control signal.
3. A power down circuit for a semiconductor memory device as claimed in claim 1 wherein said transistor switch is a PMOS transistor and said generator produces a negative voltage as said control voltage.
4. A power down circuit for a semiconductor memory device as claimed in claim 1 wherein said control voltage of linearly tracks changes in the value of said external voltage.
5. A power down circuit for a semiconductor memory device as claimed in claim 4 wherein said transistor switch is a PMOS transistor and said generator produces a negative voltage as said control voltage.
6. A power down circuit for a semiconductor memory device as claimed in claim 5 wherein the value of the control voltage becomes more positive as the value of the external voltage becomes more positive.