Nonvolatile semiconductor memory device
View Patent ↗A nonvolatile semiconductor memory device includes a memory cell array which includes memory cells and reference cells, the reference cells including a first reference cell and a second reference cell. A data discriminating control unit generates an average reference level based on a reference level supplied from the first reference cell and a reference level supplied from the second reference cell, and the data discriminating control unit determining whether data is zero or one by comparison of a read-out level of each of the memory cells with the average reference level. A reference cell setting unit performs program verification for each memory cell with respect to a threshold level of the first reference cell to obtain a distribution of threshold levels of the memory cells, and the reference cell setting unit setting a threshold level of the second reference cell based on the distribution of the threshold levels of the memory cells.
1. A nonvolatile semiconductor memory device comprising:
a memory cell array including memory cells and reference cells, the reference cells including a first reference cell and a second reference cell;
a data discriminating control unit generating an average reference level based on a reference level supplied from the first reference cell and a reference level supplied from the second reference cell, the data discriminating control unit determining read data by comparison of a read-out level of each of the memory cells with the average reference level; and
a reference cell setting unit performing program verification for each of the memory cells based on a threshold level of the first reference cell to obtain a distribution of threshold levels of the memory cells, and the reference cell setting unit setting a threshold level of the second reference cell based on the distribution of the threshold levels of the memory cells.
2. The nonvolatile semiconductor memory device of claim 1 wherein the reference cell setting unit comprises a first reference cell setting unit which sets the threshold level of the first reference cell based on a fixed threshold level of a third reference cell for program verification.
3. The nonvolatile semiconductor memory device of claim 2 wherein the reference cell setting unit comprises a second reference cell setting unit which obtains a distribution of the threshold levels of the memory cells based on the threshold level of the first reference cell by performing a program verification check of each of the memory cells.
4. The nonvolatile semiconductor memory device of claim 3 wherein the reference cell setting unit comprises a third reference cell setting unit which sets the threshold level of the second reference cell based on the distribution of the threshold levels obtained by the second reference cell setting unit.
5. The nonvolatile semiconductor memory device of claim 1 wherein the data discriminating control unit includes a third reference cell for program verification which has a fixed threshold level.
6. The nonvolatile semiconductor memory device of claim 5 wherein the data discriminating control unit acts to set the threshold level of the first reference cell by using the fixed threshold level of the third reference cell for program verification.
7. The nonvolatile semiconductor memory device of claim 1 wherein each memory cell of the memory cell array is configured to store 2 bits of information by trapping charge in a charge-trapping layer of a silicon nitride film.
8. The nonvolatile semiconductor memory device of claim 1 wherein each memory cell of the memory cell array is configured to store 2 bits of information by trapping charge in a charge-trapping layer of a silicon nitride film, and the data discriminating control unit acts to perform program verification of each memory cell when one side of bit lines of the memory cell is selected for read-out operation and the opposite side of the bit lines is in either a programmed state or an erased state.