Self trimming voltage generator
View Patent ↗Described are integrated circuit chips that are capable of self-adjusting an internal voltage of the integrated circuit chip and methods for adjusting the internal voltage of an integrated circuit chip. The methods include comparing an internally generated voltage to an external target voltage.
1. An integrated circuit chip, comprising:
a plurality of voltage generators;
a plurality of comparators for comparing externally supplied voltages to voltages generated by the voltage generators; and
a control circuit that provides signals for adjusting the voltages generated by the voltage generators to obtain predetermined constant internal voltages.
2. The integrated circuit chip of claim 1 , wherein the voltages generated by the voltage generators are adjusted by signals provided by the control circuit concurrently.
3. The integrated circuit chip of claim 1 , further comprising a memory array.
4. The integrated circuit chip of claim 3 , wherein the memory array is a dynamic random access memory (DRAM) array.
5. The integrated circuit chip of claim 1 , wherein the control circuit provides signals for adjusting the voltages generated by the voltage generators after receiving a signal from at least one of the comparators and after the integrated circuit has received a test signal from an external source.
6. The integrated circuit chip of claim 1 , wherein the voltage generators are voltage pumps or voltage dividers.
7. The integrated circuit chip of claim 1 , wherein the control circuit comprises a Built In Self Test (BIST) controller, wherein the BIST controller activates the circuit while providing signals for adjusting the voltages generated by the voltage generators.
8. A method of adjusting internal voltages of an integrated circuit chip comprising:
supplying a plurality of external voltages to a plurality of comparators on an integrated circuit chip;
supplying a plurality of internal voltages to the comparators;
comparing the external voltages to the internal voltages; and
varying the internal voltages depending upon the comparisons between the internal voltages and the external voltages to obtain predetermined constant internal voltages.
9. The method of claim 8 , wherein the integrated circuit comprises a memory array.
10. The method of claim 9 , wherein the memory array is a dynamic random access memory (DRAM) array.
11. The method of claim 9 , wherein the internal voltages are adjusted after the integrated circuit chip receives a test signal from an external source.
12. The method of claim 9 , wherein the integrated circuit chip comprises a Built In Self Test (BIST) controller, wherein the BIST controller activates an integrated circuit while providing signals for adjusting the internal voltages.
13. A method of adjusting internal voltages of a plurality of integrated circuit chips comprising:
supplying an external voltage to a plurality of integrated circuit chips;
generating a plurality of internal generated voltages;
comparing the external voltage to the internal voltages; and
adjusting the internal voltages depending upon the comparison between the internal voltage and the external voltage to obtain predetermined constant internal voltages.
14. The method of claim 13 , wherein the internal voltages are adjusted after the integrated circuit chips receive a test signal from an external source that is distributed to the integrated circuit chips.
15. The method of claim 13 , wherein the integrated circuit chips comprise memory arrays.
16. The method of claim 15 , wherein the memory arrays are dynamic random access memory (DRAM) arrays.
17. The method of claim 13 , wherein the integrated circuit chips comprise a Built In Self Test (BIST) controller, wherein the BIST controller activates an integrated circuit while providing signals for adjusting an internal voltage.