Methods for contacting conducting layers overlying magnetoelectronic elements of MRAM devices
A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.
1. A method for contacting an electrically conductive layer overlying a magnetoelectronics element, the method comprising the steps of:
forming a memory element layer overlying a dielectric region, said memory element lever having a first magnetic portion, a second magnetic portion overlying said first magnetic portion, and a separating layer disposed between said first magnetic portion and said second magnetic portion;
depositing a first electrically conductive layer overlying said memory element layer;
depositing a first dielectric layer overlying said first electrically conductive layer;
patterning and etching said first dielectric layer to form a first masking layer;
using said first masking layer, etching said first electrically conductive layer;
depositing a second dielectric layer overlying said first masking layer and said dielectric region, said second dielectric layer comprising a material different from said first dielectric layer;
removing a portion of said second dielectric layer to expose said first masking layer; and
subjecting said second dielectric layer and said first masking layer to an etching chemistry such that said first masking layer is etched at a faster rate than said second dielectric layer, said etching of said first masking layer exposing said first electrically conductive layer.
2. The method of claim 1 , said step of forming a memory element layer comprising, forming a tunnel barrier layer as said separating layer.
3. The method of claim 1 , the step of depositing said first dielectric layer comprising depositing said first dielectric layer formed of plasma-enhanced nitride and the step of depositing said second dielectric layer comprising depositing said second dielectric layer formed from tetraethyl art orthosilicate-derived silicon dioxide.
4. The method of claim 1 , wherein said step of etching said first electrically conductive layer results in an exposed portion of said memory element layer, said method further comprising the following steps performed after said step of etching said first electrically conductive layer and before said step of depositing a second dielectric layer:
depositing a third dielectric layer overlying said exposed portion of said memory element layer and said first masking layer;
patterning and etching said third dielectric layer to form a second masking layer; and
using said second masking layer, etching said exposed portion of said memory element layer.
5. The method of claim 4 , the step of removing a portion of said second dielectric layer further comprising removing a portion of said second masking layer.
6. The method of claim 1 , further comprising the step of depositing a second electrically conductive layer overlying said dielectric region before said step of forming a memory element layer.
7. The method of claim 1 , said step of removing a portion of said second dielectric layer comprising removing said portion of said second dielectric layer by one of chemical mechanical polishing, electrochemical mechanical polishing and etching.
8. The method of claim 1 , further comprising the step of depositing an interconnect layer overlying said first electrically conductive layer, said interconnect layer in electrical communication with said first electrically conductive layer.
9. The method of claim 1 , said method further comprising the following steps:
depositing a third dielectric layer overlying said second dielectric layer and said first electrically conductive layer; and
etching said third dielectric layer to form a spacer overlying a portion of said first electrically conductive layer.
10. A method for fabricating a magnetoelectronics element structure, the method comprising the steps of:
forming a first magnetic layer overlying a dielectric region;
forming a tunnel barrier layer overlying said first magnetic layer;
forming a second magnetic layer overlying said tunnel barrier layer;
depositing a first electrically conductive layer overlying said second magnetic layer;
depositing a first dielectric layer overlying said first electrically conductive layer;
patterning and etching said first dielectric layer to form a first masking layer;
using said first masking layer, etching said first electrically conductive layer, said etching of said first masking layer exposing a portion of said second magnetic layer;
transforming said exposed portion of said second magnetic layer to form an insulative inactive portion and an active portion of said second magnetic layer, said active portion comprising a portion of a magnetic tunnel junction element and said insulative inactive portion comprising an insulator;
depositing a second dielectric layer overlying said first masking layer and said insulative inactive portion of said second magnetic layer, said second dielectric layer comprising a material different from said first dielectric layer;
removing a portion of said second dielectric layer to expose said first masking layer; and
subjecting said second dielectric layer and said first masking layer to an etching chemistry such that said first masking layer is etched at a faster rate than said second dielectric layer, said etching of said first masking layer exposing said first electrically conductive layer.
11. The method of claim 10 , the step of depositing a first dielectric layer comprising depositing said first dielectric layer formed of plasma-enhanced nitride and the step of depositing a second dielectric layer comprising depositing said second dielectric layer formed from tetraethyl orthosilicate-derived silicon dioxide.
12. The method of claim 10 , further comprising the following steps after said step of transforming and before said step of depositing a second dielectric layer:
depositing a third dielectric layer overlying said first masking layer and said insulative inactive portion of said second magnetic layer;
patterning and etching said third dielectric layer to form a second masking layer; and
using said second masking layer; etching said insulative inactive portion of said second magnetic layer, said tunnel barrier layer and said first magnetic layer.
13. The method of claim 12 , the step of removing a portion of said second dielectric layer further comprising removing a portion of said second masking layer.
14. The method of claim 10 , further comprising the step of depositing a second electrically conductive layer overlying said dielectric region before said step of forming a first magnetic layer.
15. The method of claim 10 , further comprising the step of depositing an interconnect layer overlying said first electrically conductive layer, said interconnect layer in electrical communication with said first electrically conductive layer.
16. The method of claim 10 , further comprising the following steps:
depositing a third dielectric layer overlying said second dielectric layer and said first electrically conductive layer; and
etching said third dielectric layer to form a spacer overlying a portion of said first electrically conductive layer.