IP Library Granted Patent US 6,864,170
Granted Patent B2
US 6,864,170 · App. 10/432,770 · Granted Mar 8, 2005

Compact semiconductor structure

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,864,170
App. No.
10/432,770
Granted
Mar 8, 2005
Kind
B2
Abstract

A method for reducing capacitative coupling between interconnects on a semiconductor structure includes producing a first insulating layer on a semiconductor substrate and etching trenches in the first insulating layer. Metallic interconnects are formed in the trenches by metallization. The semiconductor structure is polished to remove metal from the first insulating layer, leaving behind metal in the trenches. A portion of the first insulating layer between the first and second metallic interconnects is etched so that the first and second metallic interconnects project above the first insulating layer. A second insulating layer is applied on the substrate such that the metallic interconnects project into the second insulating layer. The second insulating layer has a relative permittivity that is lower than the relative permittivity of the first insulating layer.

Claims (9)

1. A method for reducing capacitative coupling between interconnects on a semiconductor structure, the method comprising:

producing, on a semiconductor substrate, a first insulating layer having a first relative permittivity;

etching first and second trenches in the first insulating layer;

forming first and second metallic interconnects in the trenches by metallization, thereby filling the trenches with metal;

polishing the semiconductor structure to remove metal from the first insulating layer, leaving behind metal in the trenches;

etching a portion of the first insulating layer between the first and second metallic interconnects, thereby causing the first and second metallic interconnects to project above the first insulating layer; and

producing, on the semiconductor substrate, a second insulating layer having a second relative permittivity that is lower than the first relative permittivity, the first and second metallic interconnects projecting into the second insulating layer.

2. The method of claim 1 , wherein producing the first insulating layer comprises applying an oxide by chemical vapor deposition.

3. The method of claim 1 , wherein producing the first insulating layer comprises producing an insulating layer having a relative permittivity less than 3.9.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036615/0885 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023768/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2003
From: KIESLICH, ALBRECHT; WEBER, DETLEF; HOHNSDORF, FALKO
To: INFINEON TECHNOLOGIES AG
Reel/Frame 014536/0779 →