IP Library Granted Patent US 6,876,069
Granted Patent B2
US 6,876,069 · App. 10/462,264 · Granted Apr 5, 2005

Ground plane for exposed package

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Quick Facts
Patent No.
US 6,876,069
App. No.
10/462,264
Granted
Apr 5, 2005
Kind
B2
Abstract

A new design is provided for the design of a leadframe of a semiconductor package. A ground plane is added to the design of the leadframe, the ground frame is located between the leadframe and the die attach paddle over which the semiconductor device is mounted.

Claims (41)

1. An interface for mounting a semiconductor device in a semiconductor package, comprising:

a die attach paddle;

a leadframe; and

a ground plane as a physical and thereto connected interface between said die attach paddle and said lead frame, a plane of said ground plane being interposed between a plane of said die attach paddle and a plane of said lead frame, a plane of said ground plane being parallel with a plane of said die attach paddle, a plane of said ground plane further being parallel with a plane of said lead frame, said ground plane comprising separated layers of metal spatially surrounding said die attach paddle.

2. The interface of claim 1 , said physical and thereto connected interface between said die attach paddle and said lead frame comprising metal interconnects in metal strip form, a plane of said metal interconnects intersecting a plane of said die attach paddle under an angle.

3. The interface of claim 1 , said ground-plane comprising a square or rectangular geometric shape when viewed in top view.

4. A semiconductor device package, comprising:

a semiconductor device, said semiconductor device being mounted over a die attach paddle after a layer of die attach paste has been deposited over the surface of said die attach paddle;

a leadframe;

a ground plane, forming a physical and thereto connected interface between said die attach paddle and said lead frame, a plane of said ground plane being interposed between a plane of said die attach paddle and a plane of said lead frame, a plane of said ground plane being parallel with a plane of said die attach paddle, a plane of said ground plane further being parallel with a plane of said lead frame, said around plane comprising separated layers of metal spatially surrounding said die attach paddle;

first conductive interconnects having been provided between points of electrical contact on an active surface of the semiconductor die and the surface of said lead frame;

second conductive interconnects having been provided between points of electrical contact on an active surface of the semiconductor die and said ground plane; and

a mold compound overlying said die attach paddle, further enclosing said ground plane, further enclosing said first and second conductive interconnects, further enclosing said lead frame by a measurable amount.

5. The semiconductor device package of claim 4 , said first conductive interconnects being selected from the group consisting of signal wires and ground wires and power wires.

6. The semiconductor device package of claim 4 , said second conductive interconnects comprising ground wires.

7. The semiconductor device package of claim 4 , said physical and thereto connected interface between said die attach paddle and said lead frame comprising metal interconnects in metal strip form, a plane of said metal interconnects intersecting a plane of said die attach paddle under an angle.

8. The semiconductor device package of claim 4 , said ground plane comprising a square or rectangular geometric shape when viewed in top view.

9. An interface for mounting a semiconductor device in a semiconductor package, comprising:

a die attach paddle;

a leadframe; and

a ground plane as a physical and thereto connected interface between said die attach paddle and said lead frame, a plane of said ground plane being interposed between a plane of said die attach paddle and a plane of said lead frame, a plane of said ground plane being parallel with a plane of said die attach paddle, a plane of said ground plane further being parallel with a plane of said lead frame, said physical and thereto connected interface between said die attach paddle and said lead frame comprising metal interconnects in metal strip form, a plane of said metal interconnects intersecting a plane of said die attach paddle under an angle, said ground plane comprising separated layers of metal spatially surrounding said die attach paddle.

10. The interface of claim 9 , said ground plane comprising a square or rectangular geometric shape when viewed in top view.

11. A semiconductor device package, comprising:

a semiconductor device, said semiconductor device being mounted over a die attach paddle after a layer of die attach paste has been deposited over the surface of said die attach paddle;

a leadframe;

a ground plane, forming a physical and thereto connected interface between said die attach paddle and said lead frame, a plane of said ground plane being interposed between a plane of said die attach paddle and a plane of said lead frame, a plane of said ground plane being parallel with a plane of said die attach paddle, a plane of said ground plane further being parallel with a plane of said lead frame, said ground plane comprising separated layers of metal spatially surrounding said die attach paddle;

first conductive interconnects having been provided between points of electrical contact on an active surface of the semiconductor die and the surface of said lead frame, said first conductive interconnects being selected from the group consisting of signal wires and ground wires and power wires;

second conductive interconnects having been provided between points of electrical contact on an active surface of the semiconductor die and said ground plane; and

a mold compound overlying said die attach paddle, further enclosing said ground plane, further enclosing said first and second conductive interconnects, further enclosing said lead frame by a measurable amount.

12. The semiconductor device package of claim 11 , said second conductive interconnects comprising ground wires.

13. The semiconductor device package of claim 11 , said physical and thereto connected interface between said die attach paddle and said lead frame comprising metal interconnects in metal strip form, a plane of said metal interconnects intersecting a plane of said die attach paddle under an angle.

14. The semiconductor device package of claim 11 , said ground plane comprising a square or rectangular geometric shape when viewed in top view.

15. A semiconductor device package, comprising:

a semiconductor device, said semiconductor device being mounted over a die attach paddle after a layer of die attach paste has been deposited over the surface of said die attach paddle;

a leadframe;

a ground plane, forming a physical and thereto connected interface between said die attach paddle and said lead frame, a plane of said ground plane being interposed between a plane of said die attach paddle and a plane of said lead frame, a plane of said ground plane being parallel with a plane of said die attach paddle, a plane of said ground plane further being parallel with a plane of said lead frame, said ground plane comprising separated layers of metal spatially surrounding said die attach paddle;

first conductive interconnects having been provided between points of electrical contact on an active surface of the semiconductor die and the surface of said lead frame, said first conductive interconnects being selected from the group consisting of signal wires and ground wires and power wires;

second conductive interconnects having been provided between points of electrical contact on an active surface of the semiconductor die and said ground plane, said second conductive interconnects comprising ground wires; and

a mold compound overlying said die attach paddle, further enclosing said ground plane, further enclosing said first and second conductive interconnects, further enclosing said lead frame by a measurable amount.

16. The semiconductor device package of claim 15 , said physical and thereto connected interface between said die attach paddle and said lead frame comprising metal interconnects in metal strip form, a plane of said metal interconnects intersecting a plane of said die attach paddle under an angle.

17. The semiconductor device package of claim 15 , said ground plane comprising a square or rectangular geometric shape when viewed in top view.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0400. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 5, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064806/0593 →
RELEASE OF SECURITY INTEREST Recorded Jun 16, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052950/0497 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →