IP Library Granted Patent US 7,338,843
Granted Patent B2
US 7,338,843 · App. 10/477,967 · Granted Mar 4, 2008

Method for producing an electronic component, especially a memory chip

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Quick Facts
Patent No.
US 7,338,843
App. No.
10/477,967
Granted
Mar 4, 2008
Kind
B2
Abstract

A method for producing an electronic component, especially a memory chip, using a laser-induced correction to equalize an integrated circuit by means of at least one laser via in a layer at least partially covering the circuit. The component comprises a rewiring of the contact pads. The inventive method comprises the following steps: each laser via is closed by means of a separate covering layer which is to be applied locally; a rewiring extending between the local covering layers is created; the local covering layers are removed; and the laser-induced correction is carried out by means of the open laser vias.

Claims (43)

1. A method for producing an electronic component, in particular a memory chip, with a laser-indexed correction for the adjustment of an integrated circuit by means of one or more laser vias introduced into a covering layer that at least partially covers the circuit, the component having a rewiring of the contact pads, comprising the following steps:

closing off of each laser via by means of a separate thin cover layer that is to be applied locally,

production of a rewiring running between the local cover layers, and

carrying out of the laser-induced correction by means of the closed laser vias.

2. The method as claimed in claim 1 , characterized in that a reinforcing cover layer is applied to the thin cover layer after the correction.

3. The method as claimed in claim 1 , characterized in that the if appropriate first cover layer has a thickness of ≦1 μm.

4. The method as claimed in claim 1 , characterized in that the if appropriate first cover layer is resistant to a subsequent etching step that is effected in particular for the purpose of producing the rewiring.

5. A method for producing an electronic component with a laser-indexed correction for adjustment of an integrated circuit by means of a plurality of laser vias introduced into a layer that at least partially covers the circuit, comprising the following steps:

(a) providing a plurality of separate local cover layers that are to be applied locally, each local cover layer closing a respective laser via;

(b) producing a rewiring of contact pads applied to the component running between the local cover layers;

(c) removing the local cover layers to open the laser vias; and

(d) carrying out the laser-indexed correction following opening of the laser vias by means of the laser vias.

6. The method as claimed in claim 5 , wherein the laser vias are covered again by means of a covering layer after laser adjustment has been effected.

7. The method as claimed in claim 5 , wherein a cover layer that can be decomposed chemically, thermally or by irradiation is used as the cover layer.

8. The method as claimed in claim 5 , wherein printing takes place on the local cover layers.

9. The method as claimed in claim 8 , wherein printing takes place in a mask or screen printing method.

10. The method as claimed in claim 5 , wherein each cover layer comprises a polymer layer.

11. The method as claimed in claim 5 , wherein the component is tested before the local cover layers are removed.

12. A method for producing an electronic component with a laser-indexed correction for adjustment of an integrated circuit by means of a plurality of laser vias introduced into a covering layer that at least partially covers the circuit, comprising the following steps:

(a) providing a thin passivation layer to close or coat individual laser fuse lines of the component;

(b) applying a covering layer to the entire component to cover the laser vias and contact pads applied to the component;

(c) opening the laser vias and the contact pads;

(d) producing a rewiring of the contact pads running between the laser vias; and

(e) carrying out the laser-indexed correction at the laser fuse lines through the laser vias.

13. The method as claimed in claim 12 , wherein the laser vias are covered again by means of a covering layer after laser adjustment has been effected.

14. The method as claimed in claim 12 , wherein the passivation layer on the laser fuse lines has a thickness of ≦0.5 μm.

15. The method as claimed in claim 12 , wherein the passivation layer on the individual laser fuse lines is resistant to a subsequent etching step that is effected to produce the rewiring.

16. The method as claimed in claim 12 , wherein printing takes place on a reinforcing cover layer.

17. The method as claimed in claim 12 , wherein the covering layer comprises a polymer layer.

18. The method as claimed in claim 12 , wherein the component is tested before carrying out the laser-induced correction through the laser fuse lines.

19. A method for producing an electronic component with a laser-indexed correction for adjustment of an integrated circuit by means of a plurality of laser vias introduced into a covering layer that at least partially covers the circuit, comprising the following steps:

(a) providing a thin passivation layer to coat individual laser fuse lines of the component;

(b) applying a covering layer to the entire component to cover the laser vias and contact pads applied to the component;

(c) opening the contact pads;

(d) producing a rewiring of the contact pads running between the laser vias;

(e) opening the laser vias; and

(f) carrying out the laser-indexed correction at the laser fuse lines through the laser vias.

20. The method as claimed in claim 19 , wherein the laser vias are covered again by means of a covering layer after laser adjustment has been effected.

21. The method as claimed in claim 19 , wherein the passivation layer on the individual laser fuse lines has a thickness of between zero and 0.5 μm.

22. The method as claimed in claim 19 , wherein the component is tested before the carrying out of the laser-induced correction and coating of the individual laser fuse lines and/or a burn-in is carried out.

23. The method as claimed in claim 19 , wherein printing takes place on the covering layer.

24. The method as claimed in claim 19 , wherein the covering layer comprises a polymer layer.

25. The method as claimed in claim 19 , wherein the component is tested before a burn-in is carried out.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036723/0021 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023768/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 10, 2004
From: HEDLER, HARRY; IRSIGLER, ROLAND; VASQUEZ, BARBARA
To: INFINEON TECHNOLOGIES AG
Reel/Frame 015308/0190 →