Method of forming an isolation layer and method of manufacturing a trench capacitor
View Patent ↗A two-step etch process is used to form a vertical collar oxide within the upper portion of a trench capacitor. The first step uses CF 4 /SiF 4 /O 2 chemistry and ends when the bottom of the collar within the trench is opened although a thin oxide layer still remains on the surface of the PAD-nitride. The second etch step uses C 4 F 8 chemistry to completely remove the remaining silicon oxide layer. The process provides a good uniformity in thickness of the PAD-nitride layer and sufficient collar oxide thickness in the very top section of the collar oxide. The process is applicable for manufacturing deep trench capacitors for DRAM devices.
1. A method of forming an isolation layer on the sidewalls of a trench, comprising:
providing a semiconductor wafer comprising a substrate including a first isolation layer stack arranged on a main surface of the substrate and a trench arranged in the substrate;
depositing a second isolation layer on the wafer so as to cover the first isolation layer stack and sidewall and bottom surfaces of the trench;
etching the wafer with a first etch gas composition comprising the gases CF 4 and SiF 4 and O 2 ; and
etching the wafer in a second etch step subsequent to the first etch step with a second etch gas composition comprising the gas C 4 F 8 .
2. The method according to claim 1 , wherein the second etch gas composition further comprises at least one of the gases CO and O 2 .
3. The method according to claim 1 , wherein the first etch step is stopped when a portion of the second isolation layer that covers the bottom surface of the trench is removed.
4. The method according to claim 3 , wherein the first isolation stack remains covered by the second isolation layer after the first etch step is stopped.
5. The method according to claim 1 , wherein the first isolation layer stack comprises silicon nitride and the second isolation layer comprises silicon oxide.
6. The method according to claim 1 , further comprising sputter etching using O 2 to clean the surface of a capacitor electrode arranged within the trench and the surface of the first isolation layer stack from residues of the second etch step.
7. A method of manufacturing a trench capacitor, comprising:
providing a semiconductor wafer comprising a substrate including a first isolation layer stack arranged on a main surface of the substrate and a deep trench arranged in the substrate, wherein the deep trench includes a lower portion filled with silicon, a dielectric layer arranged on sidewalls of the lower portion, and an upper portion arranged above the lower portion;
depositing a second isolation layer on the wafer so as to cover the first isolation layer stack, sidewall surfaces of the upper portion of the deep trench and a bottom surface of the upper portion of the deep trench that is defined at a top surface of the silicon filling the lower portion of the deep trench;
etching the wafer with a first etch gas composition comprising the gases CF 4 and SiF 4 and O 2 ; and
etching the wafer in a second etch step subsequent to the first etch step with a second etch gas composition comprising the gas C 4 F 8 .
8. The method according to claim 7 , wherein the second isolation layer is a collar isolation and the upper portion of the deep trench is further filled with doped silicon.
9. The method according to claim 6 , wherein the sputter etching is subsequent to the second etch step.
10. The method according to claim 7 , wherein the second etch gas compositions further comprises at least one of the gases CO and O 2 .
11. The method according to claim 7 , wherein the first etch step is stopped when a portion of the second isolation layer, which is arranged on the bottom surface of the upper portion of the deep trench, is removed.
12. The method according to claim 11 , wherein the first isolation stack remains covered by the second isolation layer after the first etch step is stopped.
13. The method according to claim 7 , wherein the first isolation layer stack comprises silicon nitride and the second isolation layer comprises silicon oxide.
14. The method according to claim 7 , further comprising a sputter etching using O 2 to clean the surface of a capacitor electrode arranged within the trench and the surface of the first isolation layer stack from residues of the second etch step.
15. The method according to claim 14 , wherein the sputter etching is subsequent to the second etch step.