Testing method and tester for semiconductor integrated circuit device comprising high-speed input/output element
The invention relates to a test method and a test apparatus for a semiconductor integrated circuit device having a high-speed input/output device, and it has for its object to perform the test of the high-speed I/O exceeding 1 GHz, promptly by a simple board construction, without altering a test system for individual I/O specifications. A semiconductor integrated circuit device ( 1 ) having a high-speed input/output device ( 2 ) is set on a load board ( 3 ) which is provided with loopback paths ( 4 ) each connecting the external output terminal and external input terminal of the semiconductor integrated circuit device ( 1 ) by transmission lines, and the operation of the high-speed input/output device ( 2 ) is tested within the semiconductor integrated circuit device ( 1 ) by utilizing test means ( 5 ) disposed inside the semiconductor integrated circuit device ( 1 ), and the loopback paths ( 4 ).
1. A method for testing a semiconductor integrated circuit device having a high-speed input/output device, comprising the steps of:
setting the semiconductor integrated circuit device on a load board including a plurality of loopback paths each connecting an external output terminal and an external input terminal of the semiconductor integrated circuit device by transmission lines;
testing an operation of the high-speed input/output device of the semiconductor integrated circuit device by utilizing a test means disposed inside the semiconductor integrated circuit device, and the loopback paths, wherein the test means including:
a test pattern generation means;
a boundary scan register which transfers test patterns generated by the test pattern generation means, to the high-speed input/output device; and
a check means which accepts and checks outputs delivered through the loopback paths, through the external input terminals.
2. The method for testing the semiconductor integrated circuit device having a high-speed input/output device as defined in claim 1 , wherein the test pattern generation means is a pseudo-random pattern generator, and that the check means is an output pattern compressor.