IP Library Granted Patent US 7,251,156
Granted Patent B2
US 7,251,156 · App. 10/536,292 · Granted Jul 31, 2007

Magnetic memory architecture with shared current line

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Quick Facts
Patent No.
US 7,251,156
App. No.
10/536,292
Granted
Jul 31, 2007
Kind
B2
Abstract

The present invention relates to magnetic or magnetoresistive random access memories (MRAMs). The present invention provides an array with magnetoresistive memory cells arranged in logically organized rows and columns, each memory cell including a magnetoresistive element ( 32 A, 32 B). The matrix comprises a set of column lines ( 34 ), a column line ( 34 ) being cells of a column. A column line ( 34 ) is shared by two adjacent columns, the shared column line ( 34 ) having an area which extends a continuous conductive strip which is magnetically couplable to the magnetoresistive element ( 32 A, 32 B) of each of the memory cells of a column. A column line ( 34 ) is shared by two adjacent columns, the shared column line ( 34 ) having an area which extends over substantially the magnetoresistive elements of the two adjacent columns sharing that column line. According to the present invention, the array furthermore comprises at least one supplementary column line ( 36 A, 36 B) per column for generating a localized magnetic field in the magnetoresistive elements ( 32 A, 32 B) of one of the adjacent columns sharing the column line ( 34 ). It is an advantage of the present invention that a higher density of the memory cells can be obtained, thus reducing space required to make a MRAM memory.

Claims (23)

1. An array with magnetoresistive memory cells arranged in logically organized rows and columns, each memory cell including a magnetoresistive element, the matrix comprising

a set of column lines, the column lines provided with a flux guiding cladding layer,

a column line being a continuous conductive strip which is magnetically coupled to the magnetoresistive element of each of the memory cells of a column,

a column line being shared by two adjacent columns, the shared column line having an area which extends over substantially the magnetoresistive elements of the two adjacent columns sharing that column line, the shared column line having a height smaller than width, the array furthermore comprising at least one supplementary column line per column for generating a localized magnetic field in the magnetoresisive elements of one of the adjacent columns sharing the column line.

2. The array of claim 1 , wherein a supplementary column line forms a return current path for current carried by a column line.

3. The array of claim 1 , wherein a column line and a supplementary column line are provided at opposite sides of a column of magnetoresistive elements.

4. The array of claim 1 , wherein a column of magnetoresistive elements is placed offset in a row-direction with regard to a center of a supplementary column line.

5. The array according to claim 1 , wherein the supplementary column line is provided with a flux guiding cladding layer.

6. Non-volatile memory comprising the array with magnetoresistive memory cells of claim 1 .

7. An array with magnetoresistive memory cells arranged in logically organized rows and columns, each memory cell including a magnetoresistive element, the matrix comprising

a set of column lines, the column lines provided with flux guiding claddling layer,

a column line being a continuous conductive strip which is magnetically coupled to the magnetoresistive element of each of the memory cells of a column,

a column line being shared by two adjacent columns, the shared column line having area which extends over substantially the magnetoresistive elements of the two adjacent columns sharing that column line, the shared column line having a height smaller than width,

the array furthermore comprising at least one supplementary column line per column for generating a localized magnetic field in the magnetoresistive elements of one of the adjacent columns sharing the column line; and

a set of row lines, the row lines provided with a flux guiding cladding layer, each row line being a continuous conductive strip which is magnetically coupled to the magnetoresistive element of each of the memory cells of a row.

8. A method of writing an array with magnetoresistive memory cells arranged in logically organized rows and columns, each cell including a magnetoresistive element, comprising:

applying current to a row line,

applying current to a column line having a flux guiding cladding layer and having a height smaller than width, and shared by two columns, and

applying current to at least one supplementary column line for generating a localized magnetic field in one of the memory elements on the column line.

9. A method of manufacturing an array with magnetoresistive memory cells, comprising:

providing magnetoresistive memory cells arranged in logically organized rows and columns, each cell including a magnetoresistive element,

providing a set of column lines, the column lines having a flux guiding cladding layer, a column line being a continuous conductive strip which is magnetically coupled to the magnetoresistive element of each of the memory cells of a column, a column line being shared by two adjacent columns, the shared column line having an area which extends over substantially the magnetoresistive elements of the two adjacent columns sharing that column line, the shared column line having a height smaller than width,

providing at least one supplementary column line per column for generating a localized magnetic field in the magnetoresistive elements of one of the adjacent columns sharing the column line.

Assignments (14)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2024
From: CROCUS TECHNOLOGY SA
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 066350/0669 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2023
From: CROCUS TECHNOLOGY INC.
To: CROCUS TECHNOLOGY SA
Reel/Frame 066157/0629 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2023
From: NXP B.V.
To: CROCUS TECHNOLOGY INC.
Reel/Frame 065363/0587 →
RELEASE OF SECURITY INTEREST Recorded Oct 25, 2023
From: NXP B.V.
To: CROCUS TECHNOLOGY INC.
Reel/Frame 065334/0488 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE SPELLING OF THE CONVEYING PARTY NAME AND ADDRESS ON THE DOCUMENT. PREVIOUSLY RECORDED AT REEL: 02722 FRAME: 0049. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 25, 2023
From: CROCUS TECHNOLOGY INC.
To: NXP B.V.
Reel/Frame 065345/0304 →
RELEASE OF SECURITY INTEREST Recorded Aug 30, 2023
From: LLC "SBERBANK INVESTMENTS"
To: CROCUS TECHNOLOGY, INC.
Reel/Frame 064783/0420 →
SECURITY INTEREST Recorded Apr 13, 2018
From: CROCUS TECHNOLOGY, INC.
To: LLC "SBERBANK INVESTMENTS"
Reel/Frame 045938/0810 →
RELEASE OF SECURITY INTEREST Recorded Apr 9, 2018
From: KREOS CAPITAL IV (LUXEMBOURG) SARL
To: CROCUS TECHNOLOGY, INC.
Reel/Frame 045871/0622 →
RELEASE OF SECURITY INTEREST Recorded Apr 9, 2018
From: KREOS CAPITAL IV (LUXEMBOURG) SARL
To: CROCUS TECHNOLOGY, INC.
Reel/Frame 045865/0555 →
SECURITY INTEREST Recorded Jun 29, 2015
From: CROCUS TECHNOLOGY, INC.
To: KREOS CAPITAL IV (LUXEMBOURG) SARL
Reel/Frame 036031/0327 →
SECURITY INTEREST Recorded Oct 8, 2014
From: CROCUS TECHNOLOGY, INC.
To: KREOS CAPITAL IV (LUXEMBOURG) SARL
Reel/Frame 033917/0259 →
LIEN Recorded Nov 14, 2011
From: CROCUS TECHNOLOGY, INC.
To: NXP B.V.
Reel/Frame 027222/0049 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 13, 2008
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 021085/0959 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2005
From: BOEVE, HANS
To: KONINKLIJKE PHILIPS ELECTRONICS, N.V.
Reel/Frame 016993/0820 →