Method and device for machining a wafer, in addition to a wafer comprising a separation layer and a support layer
View Patent ↗A process and an apparatus are described for the treatment of wafers, in particular for the thinning of wafers. A wafer with a carrier layer and an interlayer arranged between the carrier layer and the wafer is also described, in which the interlayer is a plasmapolymeric layer that adheres to the wafer and adheres more strongly to the carrier layer than to the wafer.
1. Wafer ( 1 , 2 ; 1 b , 2 ; 1 c , 2 ) exhibiting a front side and a rear side, said wafer comprising a carrier layer ( 4 ) and an interlayer ( 3 ) arranged between a carrier layer ( 4 ) and a wafer, characterised in that the interlayer ( 3 ) is a plasmapolymeric layer that adheres to the wafer ( 1 , 2 ; 1 b , 2 ; 1 c , 2 ) and adheres more firmly to the carrier layer ( 4 ) than to the wafer.
2. Wafer ( 1 , 2 ; 1 b , 2 ; 1 c , 2 ) according to claim 1 , in which the wafer ( 1 , 2 ; 1 b , 2 ; 1 c , 2 ) consists essentially of silicon or doped silicon.
3. Wafer ( 1 , 2 ; 1 b , 2 ; 1 c , 2 ) according to claim 1 , in which the wafer ( 1 , 2 ; 1 b , 2 ; 1 c , 2 ) comprises on its front side an active layer ( 2 ) with electronic components and the interlayer ( 3 ) is arranged on the front side.
4. Wafer ( 1 , 2 ; 1 b , 2 ; 1 c , 2 ) according to claim 1 , in which the interlayer ( 3 ) comprises an adhesive zone ( 3 b ) adjacent to the carrier layer ( 4 ) and a dehesive zone ( 3 a ) adjacent to the wafer ( 1 , 2 ; 1 b , 2 ; 1 c , 2 ), in which the adhesive zone ( 3 b ) and the dehesive zone ( 3 a ) comprise different substances.
5. Wafer ( 1 , 2 ; 1 b , 2 ; 1 c , 2 ) according to claim 1 , in which the interlayer ( 3 ) includes on the wafer side a previously liquid precursor as an integral constituent.
6. Wafer ( 1 , 2 ; 1 b , 2 ; 1 c , 2 ) according to one of claim 1 , in which the interlayer ( 3 ) adheres to the wafer and to the carrier layer ( 4 ) at temperatures of up to at least 350° C.
7. Wafer ( 1 , 2 ; 1 b , 2 ; 1 c , 2 ) according to claim 1 , in which the interlayer ( 3 ) can be stripped in a substantially residue-free manner from the wafer.
8. Wafer ( 1 , 2 ; 1 b , 2 ; 1 c , 2 ) according to claim 1 , in which the interlayer ( 3 ) and the wafer can be mechanically detached.
9. Wafer ( 1 , 2 ; 1 b , 2 ; 1 c , 2 ) according to claim 1 , in which the carrier layer ( 4 ) comprises a polymeric material.
10. Wafer ( 1 , 2 ; 1 b , 2 ; 1 c , 2 ) according to claim 1 , in which the interlayer ( 3 ) has a thermal conductivity that is less than that of the wafer by at most 10%.