IP Library Granted Patent US 7,419,875
Granted Patent B2
US 7,419,875 · App. 10/537,518 · Granted Sep 2, 2008

Shallow trench isolation in floating gate devices

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Quick Facts
Patent No.
US 7,419,875
App. No.
10/537,518
Granted
Sep 2, 2008
Kind
B2
Abstract

The present invention provides a method for manufacturing a floating gate type semiconductor device on a substrate having a surface ( 2 ), and a device thus manufactured. The method comprises:—forming, on the substrate surface, a stack comprising an insulating film ( 4 ), a first layer of floating gate material ( 6 ) and a layer of sacrificial material ( 8 ),—forming at least one isolation zone ( 18 ) through the stack and into the substrate ( 2 ), the first layer of floating gate material ( 6 ) thereby having a top surface and side walls ( 26 ),—removing the sacrificial material ( 8 ), thus leaving a cavity ( 20 ) defined by the isolation zones ( 18 ) and the top surface of the first layer of floating gate material ( 6 ), and filling the cavity ( 20 ) with a second layer of floating gate material ( 22 ), the first layer of floating gate material ( 6 ) and the second layer of floating gate material ( 22 ) thus forming together a floating-gate ( 24 ).

Claims (19)

1. Method for manufacturing a floating gate type semiconductor device on a substrate having a surface, the method comprising:

forming, on the substrate surface, a stack comprising an insulating film, a first layer of floating gate material and a layer of sacrificial material,

forming at least one isolation zone through the stack and into the substrate, the first layer of floating gate material thereby having a top surface and side walls,

removing the sacrificial material, thus leaving a cavity defined by the isolation zones and the top surface of the first layer of floating gate material, and

filling the cavity with a second layer of floating gate material having side walls, the first layer of floating gate material and the second layer of floating gate material thus forming together a floating-gate,

wherein the isolation zones are removed so as to completely expose the side walls of the second layer of floating gate material and part of the side walls of the first layer of floating gate material.

2. Method for manufacturing a floating gate type semiconductor device on a substrate having a surface, the method comprising:

forming, on the substrate surface, a stack comprising an insulating film, a first layer of floating gate material and a layer of sacrificial material,

forming at least one isolation zone through the stack and into the substrate, the first layer of floating gate material thereby having a top surface and side walls,

removing the sacrificial material, thus leaving a cavity defined by the isolation zones and the top surface of the first layer of floating gate material,

filling the cavity with a second layer of floating gate material, the first layer of floating gate material and the second layer of floating gate material thus forming together a floating-gate, and

forming a protection layer between the first layer of floating gate material and the sacrificial layer.

3. Method for manufacturing a floating gate type semiconductor device on a substrate having a surface, the method comprising:

forming, on the substrate surface, a stack comprising an insulating film, a first layer of floating gate material and a layer of sacrificial material,

forming at least one isolation zone through the stack and into the substrate, the first layer of floating gate material thereby having a top surface and side walls,

removing the sacrificial material, thus leaving a cavity defined by the isolation zones and the top surface of the first layer of floating gate material,

filling the cavity with a second layer of floating gate material having sidewalls, the first layer of floating gate material and the second layer of floating gate material thus forming together a floating-gate,

partially removing the isolation zones so as to completely expose the side walls of the second layer of floating gate material and to partially expose the side walls of the first layer of floating gate material, and

forming a protection layer between the first layer of floating gate material and the sacrificial layer.

Assignments (15)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
PATENT RELEASE Recorded Aug 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039707/0471 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
PATENT RELEASE Recorded Apr 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.; MIZUHO BANK, LTD.
To: NXP B.V.
Reel/Frame 038400/0637 →
CERTIFICATE RE. TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS Recorded Apr 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.; MIZUHO BANK, LTD.
To: NXP B.V.
Reel/Frame 038401/0296 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2016
From: NXP B.V.
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 037973/0107 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 13, 2008
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 021085/0959 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2005
From: SCHAIJK, ROBERTUS BAN; VAN DUUREN, MICHIEL
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 017449/0826 →