Integrity control for data stored in a non-volatile memory
View Patent ↗The present invention relates to a write controller for a memory with a plurality of non-volatile storage cells, a read controller for a memory with a plurality of nonvolatile storage cells, to a combined write/read controller, to a solid state device comprising a memory with a plurality of non-volatile storage cells, a programmer device for writing a binary code to a non-volatile memory, to a method for writing data comprising at least one input bit to a memory having non-volatile storage cells, and to a method for controlling the integrity of data comprising at least one input bit stored in non-volatile storage cells of a memory. The basic concept of the present invention is to extend information stored in a non-volatile memory by at least one checking bit. The checking bit is allocated to one code bit, or to each of a plurality of code bits.
1. A write controller for a memory with a plurality of non-volatile storage cells, comprising an input for receiving input data having a plurality of input bits to be written to said memory, and being configured to generate from said input data output data and allocated address information,
wherein said output data comprises said input data and at least one checking bit allocated to each of said input bits, said checking bit having a value complementary to that of the respective input bit such that if the value of said respective input bit is one, then the value of said checking bit is zero and vice versa, and
wherein said address information allocates said checking bit to a storage cell allocated to another storage cell storing said respective input bit.
2. The write controller of claim 1 , being configured to generate address information allocating said checking bit to a storage cell neighboring the storage cell storing said respective input bit.
3. The write controller of claim 2 , wherein said output data comprises a number of checking bits allocated to each of said input bits, said number ranging between 2 and 8, and wherein said address information allocates each checking bit to a respective storage cell in a linear or matrix-like arrangement of storage cells, such that a linear or two-dimensional pattern of stored bit values is created for each set of input bit and checking bits allocated thereto.
4. The write controller of claim 1 , comprising a checking bit generator connected to said input and configured to ascertain the bit value of each of said input bits and to generate at least one checking bit.
5. The write controller of claim 1 , comprising an address information generator connected to said input and to said checking bit generator, and configured to allocate to each of said input bits and to said allocated at least one checking bit respective address information of storage cells neighboring each other.
6. A read controller for a memory with a plurality of non-volatile storage cells, comprising an input for receiving read-out data from said memory having a plurality of input bits and at least one checking bit allocated thereto, and an integrity-control unit configured to compare each of said input bits and said at least one checking bit and to provide an output signal indicating whether or not said input bit and said checking bit are complementary, said input bit and said checking bit being complementary if the input bit is one and the checking bit is zero or vice versa.
7. The read controller of claim 6 , comprising an address generator being configured to generate a read request directed to at least one selected memory cell and said at least one neighboring memory cell storing said allocated checking bit.
8. A method for writing data comprising a plurality of input bits to a memory having non-volatile storage cells, comprising the steps of
a) ascertaining a bit value of at least one checking bit allocated to each of said input bits as the bit value complementary to the bit value of that input bit, the bit values of said input bit and said checking bit being complementary if the bit value of said input bit is one and the bit value of said checking bit is zero or vice versa,
b) allocating non-volatile memory cells to each of said input bits and the respective at least one checking bit according to a predetermined allocation algorithm, and
c) writing each of said input bits and the respective at least one checking bit to the non-volatile storage cells of said memory allocated according to step b).
9. The method of claim 8 , wherein said data comprises an identifier allocated to the memory.
10. The method of claim 8 , wherein said allocation algorithm comprises allocating each of said input bits and the respective at least one checking bit to neighboring storage cells.
11. The method of claim 8 , which is performed before, during or after a test of a die containing the memory.
12. The method of claim 8 , wherein after said writing step further writing to the memory is blocked.
13. The method of claim 8 , wherein said writing step is performed after a step of providing a password and verifying the identity of the provided password with a password that is stored on a chip containing the memory.
14. A method for controlling the integrity of data comprising a plurality of input bits stored in non-volatile storage cells of a memory, comprising the steps of
a) ascertaining a bit value of at least one checking bit allocated to each of said input bits as the bit value complementary to the bit value of that input bit, the bit values of said input bit and said checking bit being complementary if the bit value of said input bit is one and the bit value of said checking bit is zero or vice versa,
b) allocating non-volatile storage cells to each of said input bits and the respective at least one checking bit according to a predetermined allocation algorithm,
c) writing each of said input bits and the respective at least one checking bit to the non-volatile storage cells allocated according to step b),
d) reading each of said input bits and the respective at least one checking bit from said allocated storage cells,
e) comparing each of said input bits and the respective at least one checking bit, and
f) providing a signal indicating whether or not each of said input bits and the respective at least one checking bit are complementary.