Dual differential-input amplifier having wide input range
View Patent ↗A dual differential-input operational amplifier that includes six PMOSFETs having their source terminals coupled to a high voltage. A seventh and eighth PMOSFET have their source terminals coupled to a current source. Four NMOSFETs have their source terminals coupled to a low voltage. A fifth and sixth NMOSFET have their source terminals coupled to a current sink. The various PMOSFETs and NMOSFETs are coupled together such that the gate terminals of the fifth NMOSFET and eighth PMOSFET receive a first input of the differential input, and such that the gate terminals of the sixth NMOSFET and the seventh PMOSFET receive a second input of the differential input. The operational amplifier may be vertically inverted, or implemented by bipolar transistors, with cascoding devices, and with a second stage in the form of an inverter.
1. A circuit comprising a dual differential-input amplifier that comprising the following:
a first PMOSFET having a source terminal coupled to a high voltage source, having a drain terminal, and having a gate terminal coupled to the drain terminal;
a second PMOSFET having a source terminal coupled to the high voltage source, having a drain terminal, and having a gate terminal;
a third PMOSFET having a source terminal coupled to the high voltage source, having a drain terminal coupled to the gate terminal of the second PMOSFET, and having a gate terminal coupled to the drain terminal of the third PMOSFET;
a fourth PMOSFET having a source terminal coupled to the high voltage source, having a drain terminal, and having a gate terminal coupled to the drain terminal of the fourth PMOSFET;
a fifth PMOSFET having a source terminal, coupled to the high voltage source, having a drain terminal, and having a gate terminal coupled to the gate terminal of the fourth PMOSFET;
a sixth PMOSFET having a source terminal coupled to the high voltage source, having a drain terminal coupled to an output terminal of the dual differential-input amplifier, and having a gate terminal coupled to the gate terminal of the first PMOSFET;
a first NMOSFET having a source terminal coupled to a low voltage source, having a drain terminal coupled to the drain terminal of the first PMOSFET, and having a gate terminal coupled to the drain terminal of the second PMOSFET;
a second NMOSFET having a source terminal coupled to the low voltage source, having a drain terminal, and having a gate terminal coupled to the drain terminal of the second NMOSFET and to the drain terminal of the second PMOSFET;
a third NMOSFET having a source terminal coupled to the low voltage source, having a drain terminal, and having a gate terminal coupled to the drain terminal of the third NMOSFET and to the drain terminal of the fifth PMOSFET;
a fourth NMOSFET having a source terminal coupled to the low voltage source, having a drain terminal coupled to the output terminal of the dual differential-input amplifier, and having a gate terminal coupled to the drain terminal of the fifth PMOSFET;
a fifth NMOSFET having a source terminal coupled to a current sink, having a drain terminal coupled to the drain terminal of the third PMOSFET, and having a gate terminal coupled to a first input terminal of the dual differential-input amplifier;
a sixth NMOSFET having a source terminal coupled to the current sink, having a drain terminal coupled to the drain terminal of the fourth PMOSFET, and having a gate terminal coupled to a second input terminal of the dual differential-input amplifier;
a seventh PMOSFET having a source terminal coupled to a current source that provides a current of approximately equal magnitude to a current drawn by the current sink, having a drain terminal coupled to the drain terminal of the second NMOSFET, and having a gate terminal coupled to the second input terminal of the dual differential-input amplifier; and
an eighth PMOSFET having a source terminal coupled to the current source, having a drain terminal coupled to the drain terminal of the third NMOSFET, and having a gate terminal coupled to the first input terminal of the dual differential-input amplifier.
2. A circuit in accordance with claim 1 , further comprising an inverter that comprises the following:
a ninth PMOSFET having a source terminal coupled to the high voltage source, having a drain terminal coupled to an output terminal of a comparator, and having a gate terminal coupled to the output terminal of the dual differential-input amplifier; and
a, seventh NMOSFET having a source terminal coupled to the low voltage source, having a drain terminal coupled to the output terminal of the comparator, and having a gate terminal coupled to the output terminal of the dual differential-input amplifier.
3. A circuit in accordance with claim 2 , further comprising the following:
a cascoded PMOSFET coupled between the sixth PMOSFET and the output terminal of the dual differential-input amplifier in a cascoded configuration.
4. A circuit in accordance with claim 3 , further comprising the following:
a cascoded NMOSFET coupled between the fourth NMOSFET and the output terminal of the dual differential-input amplifier in a cascoded configuration.
5. A circuit in accordance with claim 2 , further comprising the following:
a cascoded NMOSFET coupled between the fourth NMOSFET and the output terminal of the dual differential-input amplifier in a cascoded configuration.
6. A circuit in accordance with claim 1 , further comprising the following:
a cascoded PMOSFET coupled between the sixth PMOSFET and the output terminal of the dual differential-input amplifier in a cascoded configuration.
7. A circuit in accordance with claim 6 , further comprising the following:
a cascoded NMOSFET coupled between the fourth NMOSFET and the output terminal of the dual differential-input amplifier in a cascoded configuration.
8. A circuit in accordance with claim 1 , further comprising the following:
a cascoded NMOSFET coupled between the fourth NMOSFET and the output terminal of the dual differential-input amplifier in a cascoded configuration.
9. A circuit comprising a dual differential-input amplifier that comprising the following:
a first NMOSFET having a source terminal coupled to a low voltage source, having a drain terminal, and having a gate terminal coupled to the drain terminal;
a second NMOSFET having a source terminal coupled to the low voltage source, having a drain terminal, and having a gate terminal;
a third NMOSFET having a source terminal coupled to the low voltage source, having a drain terminal coupled to the gate terminal of the second NMOSFET, and having a gate terminal coupled to the drain terminal of the third NMOSFET;
a fourth NMOSFET having a source terminal coupled to the low voltage source, having a drain terminal, and having a gate terminal coupled to the drain terminal of the fourth NMOSFET;
a fifth NMOSFET having a source terminal coupled to the low voltage source, having a drain terminal, and having a gate terminal coupled to the gate terminal of the fourth NMOSFET;
a sixth NMOSFET having a source terminal coupled to the low voltage source, having a drain terminal coupled to an output terminal of the dual differential-input amplifier, and having a gate terminal coupled to the gate terminal of the first NMOSFET;
a first PMOSFET having a source terminal coupled to a high voltage source, having drain terminal coupled to the drain terminal of the first NMOSFET, and having a gate terminal coupled to the drain terminal of the second NMOSFET;
a second PMOSFET having a source terminal coupled to the high voltage source, having a drain terminal, and having a gate terminal coupled to the drain terminal of the second PMOSFET and to the drain terminal of the second NMOSFET;
a third PMOSFET having a source terminal coupled to the high voltage source, having a drain terminal, and having a gate terminal coupled to the drain terminal of the third PMOSFET and to the drain terminal of the fifth NMOSFET;
a fourth PMOSFET having a source terminal coupled to the high voltage source, having a drain terminal coupled to the output terminal of the dual differential-input amplifier, and having a gate terminal coupled to the drain terminal of the fifth NMOSFET;
a fifth PMOSFET having a source terminal coupled to a current source, having a drain terminal coupled to the drain terminal of the third NMOSFET, and having a gate terminal coupled to a first input terminal of the dual differential-input amplifier;
a sixth PMOSFET having a source terminal coupled to the current source, having a drain terminal coupled to the drain terminal of the fourth NMOSFET, and having a gate terminal coupled to a second input terminal of the dual differential-input amplifier;
a seventh NMOSFET having a source terminal coupled to a current sink that draws a current of approximately equal magnitude to a current supplied by the current source, having a drain terminal coupled to the drain terminal of the second PMOSFET, and having a gate terminal coupled to the second input terminal of the dual differential-input amplifier; and
an eighth NMOSFET having a source terminal coupled to the current sink, having a drain terminal coupled to the drain terminal of the third PMOSFET, and having a gate terminal coupled to the first input terminal of the dual differential-input amplifier.
10. A circuit in accordance with claim 9 , further comprising an inverter that comprises the following:
a ninth NMOSFET having a source terminal coupled to the low voltage source, having a drain terminal coupled to an output terminal of a comparator, and having a gate terminal coupled to the output terminal of the dual differential-input amplifier; and
a seventh PMOSFET having a source terminal coupled to the high voltage source, having a drain terminal coupled to the output terminal of the comparator, and having a gate terminal coupled to the output terminal of the dual differential-input amplifier.
11. A circuit in accordance with claim 10 , further comprising the following:
a cascoded NMOSFET coupled between the sixth NMOSFET and the output terminal of the dual differential-input amplifier in a cascoded configuration.
12. A circuit in accordance with claim 11 , further comprising the following:
a cascoded PMOSFET coupled between the fourth PMOSFET and the output terminal of the dual differential-input amplifier in a cascoded configuration.
13. A circuit in accordance with claim 10 , further comprising the following:
a cascoded PMOSFET coupled between the fourth PMOSFET and the output terminal of the dual differential-input amplifier in a cascoded configuration.
14. A circuit in accordance with claim 9 , further comprising the following:
a cascoded NMOSFET coupled between the sixth NMOSFET and the output terminal of the dual differential-input amplifier in a cascoded configuration.
15. A circuit in accordance with claim 14 , further comprising the following:
a cascoded PMOSFET coupled between the fourth PMOSFET and the output terminal of the dual differential-input amplifier in a cascoded configuration.
16. A circuit in accordance with claim 9 , further comprising the following:
a cascoded PMOSFET coupled between the fourth PMOSFET and the output terminal of the dual differential-input amplifier in a cascoded configuration.
17. A circuit comprising a dual differential-input amplifier that comprising the following:
a first PNP bipolar transistor having an emitter terminal coupled to a high voltage source, having a collector terminal, and having a body terminal coupled to the collector terminal;
a second PNP bipolar transistor having an emitter terminal coupled to the high voltage source, having a collector terminal, and having a body terminal;
a third PNP bipolar transistor having an emitter terminal coupled to the high voltage source, having a collector terminal coupled to the body terminal of the second PNP bipolar transistor, and having a body terminal coupled to the collector terminal of the third PNP bipolar transistor;
a fourth PNP bipolar transistor having an emitter terminal coupled to the high voltage source, having a collector terminal, and having a body terminal coupled to the collector terminal of the fourth PNP bipolar transistor;
a fifth PNP bipolar transistor having an emitter terminal coupled to the high voltage source, having a collector terminal, and having a body terminal coupled to the body terminal of the fourth PNP bipolar transistor;
a sixth PNP bipolar transistor having an emitter terminal coupled to the high voltage source, having a collector terminal coupled to an output terminal of the dual differential-input amplifier, and having a body terminal coupled to the body terminal of the first PNP bipolar transistor;
a first NPN bipolar transistor having an emitter terminal coupled to a low voltage source, having a collector terminal coupled to the collector terminal of the first PNP bipolar transistor, and having a body terminal coupled to the collector terminal of the second PNP bipolar transistor;
a second NPN bipolar transistor having an emitter terminal coupled to the low voltage source, having a collector terminal, and having a body terminal coupled to the collector terminal of the second NPN bipolar transistor and to the collector terminal of the second PNP bipolar transistor;
a third NPN bipolar transistor having an emitter terminal coupled to the low voltage source, having a collector terminal, and having a body terminal coupled to the collector terminal of the third NPN bipolar transistor and to the collector terminal of the fifth PNP bipolar transistor;
a fourth NPN bipolar transistor having an emitter terminal coupled to the low voltage source, having a collector terminal coupled to the output terminal of the dual differential-input amplifier, and having a body terminal coupled to the collector terminal of the fifth PNP bipolar transistor;
a fifth NPN bipolar transistor having an emitter terminal coupled to a current sink, having a collector terminal coupled to the collector terminal of the third PNP bipolar transistor, and having a body terminal coupled to a first input terminal of the dual differential-input amplifier;
a sixth NPN bipolar transistor having an emitter terminal coupled to the current sink, having a collector terminal coupled to the collector terminal of the fourth PNP bipolar transistor, and having a body terminal coupled to a second input terminal of the dual differential-input amplifier;
a seventh PNP bipolar transistor having an emitter terminal coupled to a current source that provides a current of approximately equal magnitude to a current drawn by the current sink, having a collector terminal coupled to the collector terminal of the second NPN bipolar transistor, and having a body terminal coupled to the second input terminal of the dual differential-input amplifier; and
an eighth PNP bipolar transistor having an emitter terminal coupled to the current source, having a collector terminal coupled to the collector terminal of the third NPN bipolar transistor, and having a body terminal coupled to the first input terminal of the dual differential-input amplifier.
18. A circuit in accordance with claim 17 , further comprising an inverter that comprises the following:
a ninth PNP bipolar transistor having an emitter terminal coupled to the high voltage source, having a collector terminal coupled to an output terminal of a comparator, and having a body terminal coupled to the output terminal of the dual differential-input amplifier; and
a seventh NPN bipolar transistor having an emitter terminal coupled to the low voltage source, having a collector terminal coupled to the output terminal of the comparator, and having a body terminal coupled to the output terminal of the dual differential-input amplifier.
19. A circuit comprising a dual differential-input amplifier that comprising the following:
a first NPN bipolar transistor having an emitter terminal coupled to a low voltage source, having a collector terminal, and having a body terminal coupled to the collector terminal;
a second NPN bipolar transistor having an emitter terminal coupled to the low voltage source, having a collector terminal, and having a body terminal;
a third NPN bipolar transistor having an emitter terminal coupled to the low voltage source, having a collector terminal coupled to the body terminal of the second NPN bipolar transistor, and having a body terminal coupled to the collector terminal of the third NPN bipolar transistor;
a fourth NPN bipolar transistor having an emitter terminal coupled to the low voltage source, having a collector terminal, and having a body terminal coupled to the collector terminal of the fourth NPN bipolar transistor;
a fifth NPN bipolar transistor having an emitter terminal coupled to the low voltage source, having a collector terminal, and having a body terminal coupled to the body terminal of the fourth NPN bipolar transistor;
a sixth NPN bipolar transistor having an emitter terminal coupled to the low voltage source, having a collector terminal coupled to an output terminal of the dual differential-input amplifier, and having a body terminal coupled to the body terminal of the first NPN bipolar transistor;
a first PNP bipolar transistor having an emitter terminal coupled to a high voltage source, having a collector terminal coupled to the collector terminal of the first NPN bipolar transistor, and having a body terminal coupled to the collector terminal of the second NPN bipolar transistor;
a second PNP bipolar transistor having an emitter terminal coupled to the high voltage source, having a collector terminal, and having a body terminal coupled to the collector terminal of the second PNP bipolar transistor and to the collector terminal of the second NPN bipolar transistor;
a third PNP bipolar transistor having an emitter terminal coupled to the high voltage source, having a collector terminal, and having a body terminal coupled to the collector terminal of the third PNP bipolar transistor and to the collector terminal of the fifth NPN bipolar transistor;
a fourth PNP bipolar transistor having an emitter terminal coupled to the high voltage source, having a collector terminal coupled to the output terminal of the dual differential-input amplifier, and having a body terminal coupled to the collector terminal of the fifth NPN bipolar transistor;
a fifth PNP bipolar transistor having an emitter terminal coupled to a current source, having a collector terminal coupled to the collector terminal of the third NPN bipolar transistor, and having a body terminal coupled to a first input terminal of the dual differential-input amplifier;
a sixth PNP bipolar transistor having an emitter terminal coupled to the current source, having a collector terminal coupled to the collector terminal of the fourth NPN bipolar transistor, and having a body terminal coupled to a second input terminal of the dual differential-input amplifier;
a seventh NPN bipolar transistor having an emitter terminal coupled to a current sink that draws a current of approximately equal magnitude to a current supplied by the current source, having a collector terminal coupled to the collector terminal of the second PNP bipolar transistor, and having a body terminal coupled to the second input terminal of the dual differential-input amplifier; and
an eighth NPN bipolar transistor having an emitter terminal coupled to the current sink, having a collector terminal coupled to the collector terminal of the third PNP bipolar transistor, and having a body terminal coupled to the first input terminal of the dual differential-input amplifier.
20. A circuit in accordance with claim 19 , further comprising an inverter that comprises the following:
a ninth NPN bipolar transistor having an emitter terminal coupled to the low voltage source, having a collector terminal coupled to an output terminal of a comparator, and having a body terminal coupled to the output terminal of the dual differential-input amplifier; and
a seventh PNP bipolar transistor having an emitter terminal coupled to the high voltage source, having a collector terminal coupled to the output terminal of the comparator, and having a body terminal coupled to the output terminal of the dual differential-input amplifier.