Low voltage transient voltage suppressor
View Patent ↗A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with reduced clamp voltages between 0.5 and 5 volts. Trench MOS based TVS device ( 72 ) provides an enhanced gain operation, while device ( 88 ) provides a top side drain contact. The high gain MOS based TVS devices provide increased control over clamp voltage variation.
1. A semiconductor device for suppressing an external transient voltage, comprising an insulated gate bipolar transistor (IGBT) having a gate terminal and a first conduction terminal coupled to receive the external transient voltage, first and second diodes coupled in a back to back fashion between the gate and first conduction terminals, and a second conduction terminal to shunt a surge current flowing through the first conduction terminal in response to the external transient voltage exceeding a predetermined level.
2. The semiconductor device of claim 1 , further comprising a semiconductor substrate having a top surface for forming the first conduction terminal and the gate terminal of the IGBT.
3. The semiconductor device of claim 2 , wherein the semiconductor substrate includes:
a body region of a first conductivity type for inverting to form a channel of the IGBT;
an emitter region formed at the top surface for receiving the surge current from the first conduction terminal; and
a drift region having a second conductivity type and coupled to the channel for conducting the surge current.
4. The semiconductor device of claim 3 , wherein the semiconductor substrate further includes a collector region of the first conductivity type formed adjacent to the drift region for routing the surge current between the drift region and the second conduction terminal.
5. The semiconductor device of claim 4 , wherein the collector region is formed on the top surface of the semiconductor substrate.
6. The semiconductor device of claim 4 , wherein the semiconductor substrate has a bottom surface for forming the collector region and the second conduction terminal.
7. The semiconductor device of claim 6 , further comprising a semiconductor package having a die flag for mounting the semiconductor substrate, wherein the collector region is electrically coupled to the die flag for routing the surge current to an external node.
8. The semiconductor device of claim 7 , wherein the semiconductor package further includes a bonding wire coupled between the gate terminal and the die flag.
9. The semiconductor device of claim 6 , further comprising a collection region of the first conductivity type that is coupled to the first conduction terminal and formed at the top surface for collecting minority carriers injected from the collector region.
10. The semiconductor device of claim 3 , wherein the first and second diodes are formed in a semiconductor layer disposed on the top surface of the semiconductor substrate.
11. The semiconductor device of claim 10 , wherein a region of the semiconductor layer overlies the channel to form the gate terminal of the IGBT.
12. The semiconductor device of claim 10 , wherein the semiconductor layer is formed with polycrystalline silicon.
13. The semiconductor device of claim 12 , wherein the external transient voltage turns on the IGET to conduct the surge current between the first and second conduction terminals at a level greater than about five amperes.
14. The semiconductor device of claim 13 , wherein the IGHT limits a magnitude of the external voltage transient to a value less than about five volts.
15. A semiconductor device for suppressing an external transient voltage, comprising an insulated gate bipolar transistor (IGBT) having a gate terminal and a first conduction terminal coupled to receive the external transient voltage and a second conduction terminal to shunt a surge current flowing through the first conduction terminal in response to the external transient voltage exceeding a predetermined level, wherein the semiconductor device further includes:
a semiconductor substrate having a top surface for forming the first conduction terminal and the gate terminal of the IGBT and a bottom surface;
a body region of a first conductivity type formed in the semiconductor substrate for inverting to form a channel of the IGBT;
an emitter region formed at the top surface for receiving the surge current from the first conduction terminal;
a drift region having a second conductivity type and coupled to the channel for conducting the surge current;
a collector region of the first conductivity type formed adjacent to the drift region for routing the surge current between the drift region and the second conduction terminal; and
a semiconductor package having a die flag for mounting the semiconductor substrate, wherein the collector region is electrically coupled to the die flag for routing the surge current to an external node.
16. The semiconductor device of claim 15 further comprising first and second diodes coupled in a back to back fashion between the gate arid first conduction terminals.