Memory device and method for selectable sub-array activation
View Patent ↗A memory device and method for selectable sub-array activation. In one preferred embodiment, a memory array is provided comprising a plurality of groups of sub-arrays and circuitry operative to simultaneously write data into and/or read data from a selected number of groups of sub-arrays. By selecting the number of groups of sub-arrays into which data is written and/or from which data is read, the write and/or read data rate is varied. Such varying can be used to prevent thermal run-away of the memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
1. A method for writing data in a memory array, the method comprising:
(a) providing a memory device comprising a memory array comprising a plurality of groups of sub-arrays and further comprising a register storing a value N representing a number of groups of sub-arrays into which data will be simultaneously written;
(b) changing the value stored in the register from N to M; and
(c) simultaneously writing data into M groups of sub-arrays.
2. The invention of claim 1 further comprising:
(d) changing the value stored in the register from M to L; and
(e) simultaneously writing data into L groups of sub-arrays.
3. The invention of claim 1 , wherein N comprises a default value.
4. The invention of claim 1 , wherein (b) is performed in response to a signal from a host device coupled with the memory device.
5. The invention of claim 1 , wherein (b) is performed in response to a command issued by a user of a host device coupled with the memory device.
6. The invention of claim 1 , wherein (b) is performed in response to a signal from temperature-based control circuitry.
7. The invention of claim 1 , wherein (b) is performed during testing of the memory array.
8. The invention of claim 1 , wherein the memory array comprises a three-dimensional memory array.
9. The invention of claim 1 , wherein the memory array comprises a plurality of antifuse memory cells.
10. The invention of claim 1 , wherein the memory array comprises a plurality of write-once memory cells.
11. The invention of claim 1 , wherein the memory array comprises a plurality of write-many memory cells.
12. A method for reading data from a memory array, the method comprising:
(a) providing a memory device comprising a memory array comprising a plurality of groups of sub-arrays and further comprising a register storing a value N representing a number of groups of sub-arrays from which data will be simultaneously read;
(b) changing the value stored in the register from N to M; and
(c) simultaneously reading data from M groups of sub-arrays.
13. The invention of claim 12 further comprising:
(d) changing the value stored in the register from M to L; and
(e) simultaneously reading data from L groups of sub-arrays.
14. The invention of claim 12 , wherein N comprises a default value.
15. The invention of claim 12 , wherein (b) is performed in response to a signal from a host device coupled with the memory device.
16. The invention of claim 12 , wherein (b) is performed in response to a command issued by a user of a host device coupled with the memory device.
17. The invention of claim 12 , wherein (b) is performed in response to a signal from temperature-based control circuitry.
18. The invention of claim 12 , wherein (b) is performed during testing of the memory array.
19. The invention of claim 12 , wherein the memory array comprises a three-dimensional memory array.
20. The invention of claim 12 , wherein the memory array comprises a plurality of antifuse memory cells.
21. The invention of claim 12 , wherein the memory array comprises a plurality of write-once memory cells.
22. The invention of claim 12 , wherein the memory array comprises a plurality of write-many memory cells.
23. A method for writing data in a memory array, the method comprising:
(a) providing a memory array comprising a plurality of groups of sub-arrays;
(b) storing a value N representing a number of groups of sub-arrays into which data will be simultaneously written;
(c) changing the stored value from N to M; and
(d) simultaneously writing data into M groups of sub-arrays.
24. The invention of claim 23 , wherein the memory array is part of a memory device comprising a register, and wherein the value is stored in the register.
25. The invention of claim 23 , wherein the value is stored in the memory array.
26. The invention of claim 23 , wherein the memory array is part of a memory device coupled with a host device, and wherein the value is stored in the host device.
27. The invention of claim 23 , wherein the memory array comprises a three-dimensional memory array.
28. The invention of claim 23 , wherein the memory array comprises a plurality of antifuse memory cells.
29. The invention of claim 23 , wherein the memory array comprises a plurality of write-once memory cells.
30. The invention of claim 23 , wherein the memory array comprises a plurality of write-many memory cells.
31. A method for writing data in a passive-element memory array, the method comprising:
(a) providing a passive-element memory array comprising a plurality of groups of sub-arrays;
(b) selecting a number of groups of sub-arrays fewer than all of the groups into which data will be simultaneously written; and
(c) simultaneously writing data into the selected number of groups of sub-arrays.
32. The invention of claim 31 , wherein each group of sub-arrays comprises a respective plurality of sub-arrays, and wherein (c) comprises simultaneously writing data into fewer than all of the sub-arrays in each of the selected number of groups of sub-arrays.
33. The invention of claim 31 , wherein each group of sub-arrays comprises a respective plurality of sub-arrays, and wherein (c) comprises simultaneously writing data into all of the sub-arrays in each of the selected number of groups of sub-arrays.
34. The invention of claim 31 , wherein each group of sub-arrays comprises a respective plurality of sub-arrays, and wherein (c) comprises simultaneously writing data into only one sub-array in each of the selected number of groups of sub-arrays.
35. The invention of claim 31 , wherein each group of sub-arrays comprises a respective plurality of sub-arrays, and wherein all of the sub-arrays in each respective group share a respective data bus.
36. The invention of claim 35 , wherein (c) comprises simultaneously writing data into fewer than all of the sub-arrays in each of the selected number of groups of sub-arrays.
37. The invention of claim 36 , wherein (c) comprises simultaneously writing data into only one sub-array in each of the selected number of groups of sub-arrays.
38. The invention of claim 31 , wherein each group of sub-arrays comprises a respective plurality of sub-arrays, and wherein (c) comprises simultaneously writing data into the same number of sub-arrays in each group.
39. The invention of claim 31 , wherein each group of sub-arrays comprises a respective plurality of sub-arrays, and wherein all of the sub-arrays are written into when writing a page of data.
40. The invention of claim 31 , wherein the selected number of groups of sub-arrays is stored in a register.
41. The invention of claim 40 , wherein the register stores a default value, and wherein the default value is overwritten by the selected number of groups of sub-arrays.
42. The invention of claim 31 , wherein the number of groups of sub-arrays is automatically selected by a host device coupled with the memory array.
43. The invention of claim 31 , wherein the number of groups of sub-arrays is manually selected by a user of a host device coupled with the memory array.
44. The invention of claim 31 , wherein the number of groups of sub-arrays is automatically selected by temperature-based control circuitry.
45. The invention of claim 31 , wherein the number of groups of sub-arrays is selected during testing of the memory array.
46. The invention of claim 31 , wherein the memory array comprises a three-dimensional memory array.
47. The invention of claim 31 , wherein the memory array comprises a plurality of antifuse memory cells.
48. The invention of claim 31 , wherein the memory array comprises a plurality of write-once memory cells.
49. The invention of claim 31 , wherein the memory array comprises a plurality of write-many memory cells.
50. A method for writing data in a write-once memory array, the method comprising:
(a) providing a write-once memory array comprising a plurality of groups of sub-arrays;
(b) selecting a number of groups of sub-arrays fewer than all of the groups into which data will be simultaneously written; and
(c) simultaneously writing data into the selected number of groups of sub-arrays.
51. The invention of claim 50 , wherein (b) is performed in user mode and not in test mode.
52. The invention of claim 50 , wherein the selected number of groups of sub-arrays is stored in a register.
53. The invention of claim 52 , wherein the register stores a default value, and wherein the default value is overwritten by the selected number of groups of sub-arrays.
54. The invention of claim 50 , wherein the number of groups of sub-arrays is automatically selected by a host device coupled with the memory array.
55. The invention of claim 50 , wherein the number of groups of sub-arrays is manually selected by a user of a host device coupled with the memory array.
56. The invention of claim 50 , wherein the number of groups of sub-arrays is automatically selected by temperature-based control circuitry.
57. The invention of claim 50 , wherein the number of groups of sub-arrays is selected during testing of the memory array.
58. The invention of claim 50 , wherein the memory array comprises a three-dimensional memory array.
59. The invention of claim 50 , wherein the memory array comprises a plurality of antifuse memory cells.
60. A method for writing data in a memory array used in a host device, the method comprising:
(a) providing a host device coupled with a memory device comprising a memory array comprising a plurality of groups of sub-arrays;
(b) selecting a number of groups of sub-arrays fewer than all of the groups into which data will be simultaneously written; and
(c) simultaneously writing data into the selected number of groups of sub-arrays.
61. The invention of claim 60 , wherein the selected number of groups of sub-arrays is stored in a register in the memory device.
62. The invention of claim 61 , wherein the register stores a default value, and wherein the default value is overwritten by the selected number of groups of sub-arrays.
63. The invention of claim 60 , wherein (b) is performed in user mode and not in test mode.
64. The invention of claim 60 , wherein (b) is performed in the field.
65. The invention of claim 64 , wherein (b) is performed in the field in response to a signal from the host device.
66. The invention of claim 64 , wherein (b) is performed in the field in response to a command issued by a user of the host device.
67. The invention of claim 64 , wherein (b) is performed in the field in response to a signal from temperature-based control circuitry in the memory device.
68. The invention of claim 60 , wherein the memory array comprises a three-dimensional memory array.
69. The invention of claim 60 , wherein the memory array comprises a plurality of antifuse memory cells.
70. The invention of claim 60 , wherein the memory array comprises a plurality of write-once memory cells.
71. The invention of claim 60 , wherein the memory array comprises a plurality of write-many memory cells.
72. A method for writing data in a write-once passive-element memory array, the method comprising:
(a) providing a host device coupled with a memory device comprising a write-once passive-element memory array comprising a plurality of groups of sub-arrays, each group of sub-arrays comprising a respective plurality of sub-arrays sharing a respective data bus;
(b) storing in a register a selected number of groups of sub-arrays fewer than all of the groups into which data will be simultaneously written; and
(c) simultaneously writing data into fewer than all the sub-arrays in each of the selected number of groups of sub-arrays.
73. The invention of claim 72 , wherein (c) comprises simultaneously writing data into only one sub-array in each of the selected number of groups of sub-arrays.
74. The invention of claim 72 , wherein (b) is performed in the field.
75. The invention of claim 74 , wherein (b) is performed in the field in response to a signal from the host device.
76. The invention of claim 74 , wherein (b) is performed in the field in response to a command issued by a user of the host device.
77. The invention of claim 74 , wherein (b) is performed in the field in response to a signal from temperature-based control circuitry in the memory device.
78. The invention of claim 72 , wherein the memory array comprises a three-dimensional memory array.
79. The invention of claim 72 , wherein the memory array comprises a plurality of antifuse memory cells.