Low gate resistance layout procedure for RF transistor devices
View Patent ↗A region on a substrate contains multiple transistors in parallel that share a single salicided polysilicon gate electrode. Above or below the gate electrode are formed multiple plugs of refractory material along the length of the gate electrode. The multiple plugs of refractory material electrically interconnect the gate signal line and the salicided polysilicon gate electrode. The plug material is selected to minimize the work function between it and the salicided polysilicon gate electrode.
1. A transistor structure, comprising:
a single gate electrode formed of silicided polysilicon,
a gate signal line, and
a plurality of conductive plugs formed of a periodic table column IVB, VB, VIB, and/or VIIB metal, each of the plurality of conductive plugs electrically interconnecting the single gate electrode in a distributed manner across a length of the single gate electrode and the gate signal line,
wherein the single gate electrode, the conductive plug, and the gate signal line are arranged vertically with respect to a substrate upon which the transistor structure is mounted.
2. The transistor structure of claim 1 , wherein the conductive plug is formed of two or more layers.
3. The transistor structure of claim 2 , wherein each of the two or more layers is formed of a different material.
4. The transistor structure of claim 1 , wherein the conductive plug has a rectangular cross section.
5. The transistor structure of claim 4 , wherein the conductive plug has a width between 120 nm and 400 nm, inclusive, a length between 120 nm and 400 nm, inclusive, and a height between 200 nm to 500 nm.
6. The transistor structure of claim 5 , wherein the conductive plug has a width of 160 nm, a length of 160 nm, and a height of 280 nm.
7. The transistor structure of claim 1 , where in the gate electrode has a generally rectangular shape.
8. The transistor structure of claim 7 , wherein the gate electrode has a length between 2 microns and 10 microns, a width between 300 nm and 1 micron, and a thickness between 120 nm and 300 nm.
9. The transistor structure of claim 8 , wherein the gate electrode has a length of 4.8 microns, a width of 420 nm, and a height of 180 nm.
10. The transistor structure of claim 1 , wherein the conductive plug is formed of chromium or molybdenum.
11. The transistor structure of claim 1 , wherein the conductive plug is formed of tungsten.
12. The transistor structure of claim 1 , wherein the gate signal line is formed of copper.
13. The transistor structure of claim 1 , wherein the gate signal line is formed of aluminum.