Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same
View Patent ↗A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.
1. A method of fabricating a dual bit charge storage device on a silicon substrate, the method comprising:
a) fabricating a layered island on the surface of the substrate with an island perimeter defining a gate region, the layered island comprising a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer;
b) removing a portion of the isolation barrier dielectric layer to form an undercut region within the gate region;
c) depositing a charge trapping material within the undercut region;
d) forming a charge trapping layer positioned between the tunnel dielectric layer and the top dielectric layer from the charge trapping material, the charge trapping layer including a source charge trapping region towards one end of the charge trapping layer, a drain charge trapping region towards an opposite end of the charge trapping layer, and an isolation barrier interposed between the source charge trapping region and the drain charge trapping region,
wherein the isolation barrier is substantially less conductive relative to the source charge trapping region and the drain charge trapping region, and functions to reduce charge spread through the charge trapping layer between the source charge trapping region and the drain charge trapping region.
2. The method of claim 1 , further comprising implanting buried bit lines within the substrate on opposing sides of the layered island.
3. The method of claim 1 , wherein the charge trapping material is a silicon nitride compound.
4. The method of claim 3 , wherein the step of depositing a charge trapping material in the undercut region comprises:
depositing a layer of the silicon nitride compound on the surface of the wafer using a vapor deposition process;
performing an anisotropic etch to remove the layer of the silicon nitride compound from the horizontal surface.
5. The method of claim 1 , wherein:
the tunnel dielectric layer comprises a material with a low hydrofluoric acid etch rate; and
the step of removing a portion of the isolation barrier dielectric layer to form an undercut region within the gate region comprised performing an isotropic etch using dilute hydrofluoric acid.
6. The method of claim 5 , wherein the under cut region extends between 300 A and 500 A into the gate region.
7. The method of claim 1 , wherein the isolation barrier dielectric comprises silicon dioxide and has a thickness of between 50 A and 100 A.
8. The method of claim 1 , wherein the top dielectric layer is a compound with a dielectric constant greater than silicon dioxide and greater than the dielectric constant of the tunnel dielectric layer.
9. The method of claim 8 , wherein the top dielectric layer is a compound selected from the group of Al 2 O 3 , HfSiO x , HfO 2 , and ZrO 2 .
10. The method of claim 9 , wherein the top dielectric layer has a thickness of between 70 A and 130 A.
11. A method of fabricating a dual bit charge storage device on a silicon substrate, the method comprising:
depositing a tunnel dielectric layer on the surface of the substrate; depositing an isolation barrier dielectric layer on the surface of the tunnel dielectric layer;
depositing a top dielectric layer on the surface of the isolation barrier dielectric layer;
depositing a polysilicon gate layer on the surface of the top dielectric layer;
masking a gate pattern on the surface of the polysilicon gate layer to define a gate region and expose a non-gate region;
removing the polysilicon gate layer, the top dielectric layer, the isolation barrier dielectric layer and the tunnel dielectric layer in the non-gate region;
removing a portion of the isolation barrier dielectric layer to undercut the gate region and define undercut regions;
depositing a charge trapping material within the undercut regions; and
forming a charge trapping layer positioned between the tunnel dielectric layer and the top dielectric layer from the charge trapping material, the charge trapping layer including a source charge trapping region towards one end of the charge trapping layer, a drain charge trapping region towards an opposite end of the charge trapping layer, and an isolation barrier interposed between the source charge trapping region and the drain charge trapping region,
wherein the isolation barrier is substantially less conductive relative to the source charge trapping region and the drain charge trapping region, and functions to reduce charge spread through the charge trapping layer between the source charge trapping region and the drain charge trapping region.
12. The method of claim 11 , further comprising implanting buried bit lines on opposing sides of the gate region.
13. The method of claim 11 , wherein the charge trapping material is a silicon nitride compound.
14. The method of claim 13 , wherein the step of depositing a charge trapping material within the undercut region comprises:
depositing a layer of the silicon nitride compound on the surface of the wafer using a vapor deposition process;
performing an anisotropic etch to remove the layer of the silicon nitride compound from horizontal surfaces.
15. The method of claim 11 , wherein:
the tunnel dielectric layer comprises a material with a low hydrofluoric acid etch rate; and
the step of removing a portion of the isolation barrier dielectric layer to undercut the gate region comprises performing an isotropic etch using dilute hydrofluoric acid.
16. The method of claim 15 , wherein the under cut region extends between 300 A and 500 A into the gate region.
17. The method of claim 11 , wherein the isolation barrier dielectric comprises silicon dioxide and has a thickness of between 50 A and 100 A.
18. The method of claim 11 , wherein the top dielectric layer is a compound with a dielectric constant greater than silicon dioxide and greater than the dielectric constant of the tunnel dielectric layer.
19. The method of claim 18 , wherein the top dielectric layer is a compound selected from the group of Al 2 O 3 , HfSiO x , HfO 2 , and ZrO 2 .
20. The method of claim 19 , wherein the top dielectric layer has a thickness of between 70 A and 130 A.