Patent Assignment
Reel/Frame 019047/0566
Assignment of Assignor's Interest
Recorded: 2007-03-22
Received: 2007-03-22
Pages: 6
Assignor
ADVANCED MICRO DEVICES, INC.
Executed: 2007-01-31
Assignee
SPANSION INC.
915 DEGUIGNE DRIVE, P.O. BOX 3453, MAIL STOP 250, SUNNYVALE, CA, 94088-3453, UNITED STATES
Covered Properties
(36)
Fully Isolated Dielectric Memory Cell Structure for a Dual Bit Nitride Storage Device and Process for Making Same
Application:
10/997,345 →
Electromechanical Driver and Remote Surgical Instrument Attachment Having Computer Assisted Control Capabilities
Application:
10/761,491 →
Fully Isolated Dielectric Memory Cell Structure for a Dual Bit Nitride Storage Device and Process for Making Same
Application:
10/631,199 →
Method of Programming a Memory Cell
Application:
10/379,885 →
Reduced Silicon Gouging and Common Source Line Resistance in Semiconductor Devices
Application:
10/358,756 →
Performance in Flash Memory Devices
Application:
10/358,866 →
Treatment of Dielectric Material to Enhance Etch Rate
Application:
10/331,938 →
Method and System for Reducing Contact Defects Using Non Conventional Contact Formation Method for Semiconductor Cells
Application:
10/316,569 →
Method of Programming in-Series Memory Cells
Application:
10/282,847 →
Memory Device and Method of Making
Application:
10/223,920 →
Memory Device and Method of Making
Application:
10/189,651 →
Method for Semiconductor Wafer Planarization by Isolation Material Growth
Application:
10/190,002 →
Method for Semiconductor Wafer Planarization by Cmp Stop Layer Formation
Application:
10/190,397 →
Use of High-K Dielectric Material for Ono and Tunnel Oxide to Improve Floating Gate Flash Memory Coupling
Application:
10/176,594 →
Shallow Trench Isolation Fill Process
Application:
10/174,550 →
High Density Dual Bit Flash Memory Cell with Non Planar Structure
Application:
10/164,895 →
Hard Mask Removal Process Including Isolation Dielectric Refill
Application:
10/165,837 →
Method and System for Determining Flow Rates for Contact Formation
Application:
10/165,383 →
Method of Forming Low Resistance Common Source Line for Flash Memory Devices
Application:
10/152,747 →
Non-Volatile Memory Dielectric as Charge Pump Dielectric
Application:
10/147,622 →
Self-Aligned Polysilicon Polish
Application:
10/150,204 →
Method and System for Scaling Nonvolatile Memory Cells
Application:
10/150,255 →
Method for Minimizing Nitride Residue on a Silicon Wafer
Application:
10/150,282 →
Isolation Trench Fill Process
Application:
10/120,116 →
Stacked Polysilicon Layer for Boron Penetration Inhibition
Application:
10/118,363 →
Precision High-K Intergate Dielectric Layer
Application:
10/117,818 →
A Test Structure Apparatus for Measuring Standby Current in Flash Memory Devices
Application:
10/112,976 →
Use of High-K Dielectric Material in Modified Ono Structure for Semiconductor Devices
Application:
10/097,912 →
Memory Array with Buried Bit Lines
Application:
10/095,512 →
Method of Matching Core Cell and Reference Cell Source Resistances
Application:
10/083,789 →
Planar Transistor Structure Using Isolation Implants for Improved Vss Resistance and for Process Simplification
Application:
10/032,646 →
Shallow Trench Isolation Spacer for Weff Improvement
Application:
10/032,630 →
Fully Isolated Dielectric Memory Cell Structure for a Dual Bit Nitride Storage Device and Process for Making Same
Application:
10/027,253 →
Method for Manufacturing Memory with High Conductivity Bitline and Shallow Trench Isolation Integration
Application:
10/022,292 →
Flash Memory with Controlled Wordline Width
Application:
10/023,436 →
Reduction of Sector Connecting Line Capacitance Using Staggered Metal Lines
Application:
10/013,902 →