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App. No. 10/022,292 · Confirmation No. 1705

METHOD FOR MANUFACTURING MEMORY WITH HIGH CONDUCTIVITY BITLINE AND SHALLOW TRENCH ISOLATION INTEGRATION

Patent Expired Due to NonPayment of Maintenance Fees Under 37 CFR 1.362 View Patent ↗
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 Code Description Pages PDF
2004-03-04 IFEE Issue Fee Payment (PTO-85B) 3 View
2003-12-29 NOA Notice of Allowance and Fees Due (PTOL-85) 3 View
2003-12-29 NOA Notice of Allowance and Fees Due (PTOL-85) 3 View
2003-12-29 892 List of references cited by examiner 1 View
2003-12-29 IIFW Issue Information including classification, examiner, name, claim, renumbering, etc. 1 View
2003-12-29 SRFW Search information including classification, databases and other search related notes 1 View
2001-12-15 TRNA Transmittal of New Application 2 View
2001-12-15 ADS Application Data Sheet 1 View
2001-12-15 SPEC Specification 11 View
2001-12-15 CLM Claims 5 View
2001-12-15 ABST Abstract 1 View
2001-12-15 DRW Drawings-only black and white line drawings 5 View
2001-12-15 OATH Oath or Declaration filed 2 View
2001-12-15 TRNA Transmittal of New Application 2 View
2001-12-15 ADS Application Data Sheet 1 View
2001-12-15 SPEC Specification 11 View
2001-12-15 CLM Claims 5 View
2001-12-15 ABST Abstract 1 View
2001-12-15 DRW Drawings-only black and white line drawings 5 View
2001-12-15 OATH Oath or Declaration filed 2 View
2001-12-15 WFEE Fee Worksheet (SB06) 1 View
2001-12-15 WFEE Fee Worksheet (SB06) 1 View
2001-12-15 WCLM Claims Worksheet (PTO-2022) 1 View
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Quick Facts
App. No.
10/022,292
Filed
2001-12-15
Granted
2004-04-20
Art Unit
2812
PTA
0 days