Reduced silicon gouging and common source line resistance in semiconductor devices
View Patent ↗In the present method of undertaking a self aligned source etch of a semiconductor structure, a substrate has oxide thereon. First and second adjacent stacked gate structures are provided on the substrate. Oxide spacers are provided on the respective first and second adjacent sides of the first and second gate stacked structures, and polysilicon spacers are provided on the respective oxide spacers. A self aligned source etch is undertaken using the gate structures, oxide spacers, and polysilicon spacers as a mask. The polysilicon spacers are then removed, and metal, for example cobalt, is provided on the substrate, using the oxide spacers as a mask. A silicidation step is undertaken to form metal silicide common source line on the substrate.
1. A method of undertaking a self aligned source etch in a semiconductor structure comprising:
providing a substrate having oxide thereon;
providing first and second adjacent stacked gate structures on the substrate;
providing first and second polysilicon spacers associated with first and second adjacent sides of the first and second stacked gate structures respectively; and
etching the oxide on the substrate, using the first and second gate structures and first and second polysilicon spacers as a mask.
2. The method of claim 1 and further comprising the step of providing first and second dielectric spacers on the respective first and second adjacent sides of the first and second gate structures, the first and second polysilicon spacers being provided on the first and second dielectric spacers respectively.
3. The method of claim 2 wherein the dielectric spacers are oxide spacers.
4. The method of claim 3 and further comprising a method of forming a common source line on the substrate comprising, subsequent to said oxide etch, removing the polysilicon spacers, and, using the oxide spacers as a mask, providing metal on the substrate and undertaking a silicidation step to form metal silicide on the substrate.
5. The method of claim 4 and further comprising providing a metal on the substrate and on the oxide spacers, and undertaking a silicidation step to form metal silicide on the substrate.
6. The method of claim 5 and further comprising removing unreacted metal from the oxide spacers subsequent to undertaking the silicidation step to form metal silicide on the substrate.
7. A method of undertaking a self aligned source etch and forming a common source line in a semiconductor structure comprising:
providing a substrate having oxide thereon;
providing first and second adjacent stacked gate structures on the substrate;
providing first and second dielectric spacers on the respective first and second adjacent sides of the first and second stacked gate structures;
providing first and second polysilicon spacers on the first and second dielectric spacers respectively;
etching the oxide on the substrate using the first and second gate structures, first and second dielectric spacers, and first and second polysilicon spacers as a mask;
removing the polysilicon spacers;
providing metal on the substrate, using the dielectric spacers as mask, and on the dielectric spacers; and
undertaking a silicidation step to form metal silicide on the substrate.
8. The method of claim 7 and further comprising removing unreacted metal from the dielectric spacers subsequent to undertaking the silicidation step to form metal silicide on the substrate.
9. The method of claim 8 wherein the dielectric spacers are oxide spacers.