Multiple stacked-chip packaging structure
View Patent ↗The invention provides a multiple stacked-chip packaging structure, including: at least one lower layer chip located on a substrate, wherein a plurality of wires are electrically connected to the bonding pads on the lower layer chip and to the substrate; at least one carrier cap provided on the lower layer chip to provide an accommodating space to the bonding pads and the wires on the lower layer chip; at least one upper layer chip provided on the carrier cap, wherein a plurality of wires are electrically connected to the bonding pads on the upper layer chip and to the substrate; and finally, a Molding Compound used to wrap up the foregoing components. The advantages of the invention are that the invention is not limited by the layout patterns of bonding pads on the chip, that the needed chips can be placed on either the upper layer or the lower layer structure according to the requirement, and that the degree of coplanar can be ensured when performing wire bonding on the upper layer chip so as to facilitate the wire bonding process.
1. A multiple stacked-chip packaging structure, including:
a substrate;
at least one lower layer chip located on and in contiguous contact with the substrate, wherein a plurality of wires are respectively electrically connected to a plurality of bonding pads on the lower layer chip and to the substrate;
at least one carrier cap located on the lower layer chip and having an open cavity overlaying at least a portion of the plurality of bonding pads to provide an accommodating space to the bonding pads and the wires, the carrier cap having open sides in open communication with the accommodating space for passage of the wires therethrough;
at least one upper layer chip located on an upper surface of the carrier cap, wherein a plurality of wires are respectively electrically connected to a plurality of bonding pads on the upper layer chip and to the substrate; and
a molding compound to encapsulate the foregoing components.
2. The multiple stacked-chip packaging structure as claimed in claim 1 , wherein layout patterns of bonding pads on the upper layer chip and the lower layer chip can be classified into three categories: peripheral type, middle type, and mixed type.
3. The multiple stacked-chip packaging structure as claimed in claim 1 , wherein the carrier cap is made of thermal conductive material.
4. A multiple stacked-chip packaging structure, comprising:
a substrate;
at least one lower layer chip located on the substrate, wherein a plurality of wires are respectively electrically connected to a plurality of bonding pads on the lower layer chip and to the substrate;
at least one carrier cap having an n-shaped structure and being located on the lower layer chip to provide an accommodating space to the bonding pads and the wires;
at least one upper layer chip located on the upper surface of the carrier cap, wherein a plurality of wires are respectively electrically connected to a plurality of bonding pads on the upper layer chip and to the substrate; and
a molding compound to encapsulate the foregoing components.
5. A multiple stacked-chip packaging structures, comprising:
a substrate;
at least one lower layer chip located on the substrate, wherein a plurality of wires are respectively electrically connected to a plurality of bonding pads on the lower layer chip and to the substrate;
at least one carrier being located on the lower layer to provide an accommodating space to the bonding pads and the wires, the carrier cap being formed by a supporting set and a plurality of supporting columns, the supporting columns being provided on the lower layer chip to bear the supporting set;
at least one upper layer chip supported on the supporting set, wherein a plurality of wires are respectively electrically connected to a plurality of bonding pads on the upper layer chip and to the substrate; and
a molding compound to encapsulate the foregoing components.