Phase detector
View Patent ↗A phase detector has a reference signal input for a reference signal and a detector input for a signal to be evaluated. A memory unit is connected to the detector input and stores a state of the signal to be evaluated at a storage instant. An evaluation unit is connected downstream of the storage unit and is designed in such a way that it can be used to compare the stored state of the signal with the state of the reference signal at an evaluation instant and to generate an evaluation result signal therefrom. The phase detector has a control unit for prescribing the storage instant and the evaluation instant, the control unit prescribing the storage instant first and then the evaluation instant. A detector output is connected to the evaluation unit and the evaluation result signal can be tapped off at the detector output.
1. A phase detector, comprising:
a reference signal input for receiving a reference signal and a detector input for receiving a signal to be evaluated;
a memory unit connected to said detector input for storing a state of the signal to be evaluated at a storage instant, said memory unit having a first memory device and a second memory device;
said first memory device having a first input for receiving and storing the signal to be evaluated;
said second memory device having a first input for receiving and storing an inverted version of the signal to be evaluated;
each of said first and second memory devices having a second input for receiving a signal prescribing the storage instant;
an evaluation unit connected downstream of said memory unit, in a signal flow direction, and adapted to compare the stored state of the signal to be evaluated and the stored state of the inverted signal to be evaluated at an evaluation instant according to the reference signal to generate an evaluation result signal therefrom;
a control unit for prescribing the storage instant and the evaluation instant, said control unit being connected to said memory unit and to said evaluation unit and configured to first prescribe the storage instant and subsequently prescribe the evaluation instant; and
an output connected to said evaluation unit and carrying the evaluation result signal.
2. The phase detector according to claim 1 , wherein each of said first and second memory devices has a flip-flop for storage purposes.
3. The phase detector according to claim 1 , wherein:
each of said first and second memory devices has two NAND gates; and
for each memory device, each of said NAND gates has gate inputs and a gate output, and each said NAND gate output is connected back to one of said gate inputs of the respective other NAND gate.
4. The phase detector according to claim 1 , wherein said memory unit is configured to be operated for storing the state of the signal to be evaluated in an event of a rising edge of a signal prescribing the storage instant.
5. The phase detector according to claim 1 , wherein said evaluation unit comprises a clock-state-controlled RS flip-flop.
6. The phase detector according to claim 5 , wherein said clock-state-controlled RS flip-flop has two flip-flop inputs connected to outputs of the first memory device and the second memory device.
7. The phase detector according to claim 5 , wherein said detector comprises a flip-flop connected downstream of said clock-state-controlled RS flip-flop.
8. The phase detector according to claim 5 , wherein:
said control unit is configured to generate a delayed signal for defining the evaluation instant; and
said clock-state-controlled RS flip-flop has an input for clock state control, and said input is connected to receive the delayed signal.
9. The phase detector according to claim 1 , which comprises a further flip-flop having an input connected to the outputs of said memory unit and configured to suppress an offset.
10. The phase detector according to claim 1 , wherein said control unit has inverters for generating a signal delay.