Shift register chain for trimming generators for an integrated semiconductor apparatus
View Patent ↗An integrated semiconductor apparatus includes at least one fuse box device that includes fuses for storing trimming data, a fuse box trimming output, and a timer emitting a clock signal. The apparatus also includes a parallel/serial converter that is connected to the fuses and to the timer. The parallel/serial converter is configured to read, in parallel, the trimming data from the fuses and to emit, in serial, the trimming data from the fuse block trimming output based on the clock signal. The apparatus also includes generators. Each generator generates a generator signal and includes a trimming unit that has a trimming signal input. The trimming unit is configured to trim the generator signal of the generator based on the trimming data received. The generator also includes a trimming signal output and memory flip-flops that connect the trimming input signal to the trimming output signal. Each of the memory flip-flops connects each trimming unit to the fuse block trimming output to form a shift register chain for serial transmission of the trimming data from the fuse block device to the generators.
1. An integrated semiconductor apparatus comprising:
at least one fuse box device comprising fuses for storing trimming data, a fuse box trimming output, and a timer emitting a clock signal;
a parallel/serial converter connected to the fuses and to the timer; the parallel/serial converter being configured to read, in parallel, the trimming data from the fuses and to emit, in serial, the trimming data from the fuse block trimming output based on the clock signal;
generators, each generator generating a generator signal, each generator comprises:
a trimming unit having a trimming signal input, the trimming unit being configured to trim the generator signal of the generator based on the trimming data received;
a trimming signal output;
memory flip-flops connecting the trimming input signal to the trimming output signal; and
wherein each of the memory flip-flops connects each trimming unit to the fuse block trimming output to form a shift register chain for serial transmission of the trimming data from the at least one fuse block device to the generators.
2. The apparatus of claim 1 , wherein the trimming signal input is connected from one of the generators to the fuse block trimming output; and
wherein the trimming signal inputs of the other generators are each connected in a chain to one of the trimming signal outputs.
3. The apparatus of claim 1 , wherein each generator is a voltage generator and the generator signal is an output voltage, and wherein the trimming unit trims the output voltage based on the trimming data.
4. The apparatus of claim 1 , wherein the generator is a delay generator and wherein the generator signal is a time-delayed signal, and wherein the trimming unit trims the time delay of the time-delayed signal based on the trimming data.
5. The apparatus of claim 1 , wherein each generator further comprises a clock input; and wherein the fuse block device further comprises a fuse block clock output for emitting the clock signal from the timer to the clock input of each generator.
6. The apparatus of claim 1 , wherein the parallel/serial converter emits pulse-width modulated trimming data.
7. The apparatus of claim 1 , wherein the fuses are electrically-programmable.
8. The apparatus of claim 1 , wherein the fuses are laser-programmable.
9. The apparatus of claim 1 , wherein the integrated semiconductor apparatus comprises an integrated semiconductor memory.
10. The apparatus of claim 1 , wherein the integrated semiconductor apparatus comprises an integrated logic circuit.
11. A method of trimming generator signals generated from generators, comprising:
reading, in parallel, stored trimming data for generators;
connecting to each generator to form a shift register chain for serial transmission of the trimming data to the generators;
emitting, in serial, the trimming data based on a clock signal; and
trimming each generator signal based on the trimming data received.
12. The method of claim 11 , wherein each generator comprises a trimming signal input and a trimming signal output, and further comprising;
connecting trimming data to the trimming data input of one of the generators; and
connecting, in a chain, the trimming signal inputs of the other generators to one of the trimming signal outputs.
13. The method of claim 11 , wherein each generator is a voltage generator and the generator signal is an output voltage, and wherein timing the generator signal comprises trimming the output voltage based on the trimming data.
14. The method of claim 11 , wherein the generator is a delay generator and wherein the generator signal is a time-delayed signal, and wherein trimming the generator signal comprises trimming the time delay of the time-delayed signal based on the trimming data.
15. The method of claim 11 , further comprising sending the clock signal to each generator.
16. The method of claim 11 , wherein emitting comprises emitting pulse-width modulated trimming data.
17. The method of claim 11 , wherein the fuses are electrically-programmable.
18. The method of claim 11 , wherein the fuses are laser-programmable.
19. The method of claim 11 , wherein the integrated semiconductor apparatus comprises an integrated semiconductor memory.
20. The method of claim 11 , wherein the integrated semiconductor apparatus comprises an integrated logic circuit.