IP Library Granted Patent US 6,919,624
Granted Patent B2
US 6,919,624 · App. 10/650,433 · Granted Jul 19, 2005

Semiconductor device with exposed electrodes

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Quick Facts
Patent No.
US 6,919,624
App. No.
10/650,433
Granted
Jul 19, 2005
Kind
B2
Abstract

It is difficult to check the mounted state of solder by means of visual inspection after the mounting of a semiconductor device according to a conventional art, in particular, a CSP-semiconductor device, to a substrate and a problem arises wherein defective products increase and yield decreases. Terminals 50, 51, 52 and 53 for external connection are exposed from second main surface 412 of first insulating substrate 41 in the semiconductor device according to the present invention. Thus, second insulating substrate 48 is adhered to second main surface 412 so as to surround the internal portions of these terminals for external connection. Thereby, second insulating substrate 48 serves as a background mirror so that the mounted state of deep portions of the solder can be ascertained at the time of visual inspection of the mounted state of solder after the mounting of the semiconductor device to the substrate. As a result, the mounted state of the solder can be inspected without failure so that reduction in the number of defective products and increased yield can be attained.

Claims (28)

1. A semiconductor device, comprising:

a first substrate formed of an insulating material having at least one through hole;

a semiconductor element secured to a desired position of a conductive pattern formed on a first main surface of the first substrate;

a plurality of electrodes for external connection on a second main surface of the first substrate located opposite to the first main surface of the first substrate that is electrically connected to the desired conductive pattern via the through hole;

a resin mold formed so as to cover, at least, the main surfaces of the first substrate,

wherein the semiconductor device is characterized in that a second substrate formed of an insulating material having approximately a same coefficient of linear expansion as the first substrate is adhered to the second main surface of the first substrate so that, at least, the electrodes are exposed; and

wherein a portion of the second substrate passes between at least two of the electrodes and extends from the second main surface at least as far as the electrodes extend from the second main surface.

2. The semiconductor device according to claim 1 , wherein the second substrate is adhered to the first substrate so that, at least, the sides of the electrodes located in the vicinity of outer sides of the second main surface of the first substrate are exposed from the outer sides.

3. The semiconductor device according to claim 1 , wherein the second substrate separates the electrodes from each other so that the electrodes exist independently in separate regions.

4. The semiconductor device according to claim 2 , wherein the second substrate is thicker than the electrodes for external connection.

5. The semiconductor device according to claim 2 , wherein the electrodes are plated with gold.

6. The semiconductor device according to claim 2 , wherein the first and second substrates are ceramic substrates.

7. The semiconductor device according to claim 2 , wherein the second substrate separates the electrodes from each other so that the electrodes exist independently in separate regions.

8. The semiconductor device according to claim 3 , wherein the second substrate is thicker than the electrodes.

9. The semiconductor device according to claim 3 , wherein the electrodes are plated with gold.

10. The semiconductor device according to claim 3 , wherein the first and second substrates are ceramic substrates.

11. The semiconductor device according to claim 1 , comprising a metal wire to electrically connect an electrode pad of the semiconductor element to the desired conductive pattern.

12. A method for forming a semiconductor device, comprising:

adhering a second substrate to a second surface of a first substrate;

subsequently mounting a semiconductor element on a first surface of the first substrate; and

electrically coupling the semiconductor element to one or more electrodes on the second surface of the first substrate,

wherein the electrodes are exposed;

wherein adhering the second substrate comprises positioning the second substrate such that a portion of the second substrate passes between at least two of the electrodes and extends from the second surface at least as far as the electrodes extend from the second surface.

13. The method of claim 12 , wherein a thickness of the second substrate is greater than a thickness of the electrode.

14. The method of claim 12 , wherein a coefficient of expansion of the first substrate and a coefficient of expansion of the second substrate are substantially equal.

15. The semiconductor device according to claim 1 , wherein the portion of the second substrate extends from the second main surface farther than the electrodes extend from the second main surface.

16. The semiconductor device according to claim 1 , wherein the second main surface defines an outer periphery thereof and wherein each terminal is exposed at the second main surface at a position that is a distance inside the outer periphery.

17. The semiconductor device according to claim 16 , wherein the distance is between approximately 0.05 mm and 0.1 mm.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2014
From: KANTO SANYO SEMICONDUCTOR CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033713/0296 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2003
From: TANI, TAKAYUKI; SHIBUYA, TAKAO
To: SANYO ELECTRIC CO., LTD.; KANTO SANYO SEMICONDUCTORS CO., LTD.
Reel/Frame 014731/0747 →