Arrangement and method for ESD protection
View Patent ↗An arrangement ( 200 ) and method for scalable ESD protection of a semiconductor structure ( 140 ), a protection structure ( 120 ) providing a discharge transistor ( 110 ) path from an input/output node ( 130 ) to ground or another node if a threshold voltage is reached, wherein the discharge transistor is a self-triggered transistor having collector/drain ( 220 ) and emitter/source ( 210 ) regions, and a base/bulk region ( 260 ) having one or more floating regions ( 240 ) between the collector/drain ( 220 ) and emitter/source ( 210 ) regions. The floating region (N or P) modulates the threshold voltage Vtl for ESD protection. Vtl can be adjusted by shifting the floating region location. Splitting of the electric field into two parts reduces the maximum of the electric field. Vt 1 can be adjusted volt-by-volt to suit application needs. ESD capability is increased by better current distribution in the silicon. This provides the advantages of reduced die size, faster time-to-market, less redesign cost, and better ESD performance.
1. A voltage protection arrangement for use to protect a semiconductor structure from electro-static discharge voltage at an input node thereof, the arrangement comprising:
discharge means, having an input for coupling to the input node, and an output for coupling to ground, the discharge means being arranged to provide a discharge path from the input node to ground if the voltage at the input node exceeds a threshold voltage,
wherein the discharge means comprises self-triggered transistor means having one of:
collector and emitter regions if said self-triggered transistor means comprises bipolar transistor means, and
drain and source regions if said self-triggered transistor means comprises MOS transistor means, and
at least one floating region therein ranged to modify a threshold voltage by separating an electric field between one of:
the collector and emitter regions when the self-triggered transistor means comprises bipolar transistor means, and
the drain and source regions when the self-triggered transistor means comprises MOS transistor means.
2. The voltage protection arrangement of claim 1 wherein one of:
when the self-triggered transistor means comprises bipolar transistor means, the bipolar transistor means has a grounded base, and
when the self-triggered transistor means comprises MOS transistor means, the MOS transistor means has a grounded gate.
3. The voltage protection arrangement of claim 1 wherein, when the self-triggered transistor means comprises MOS transistor means, the MOS transistor means is arranged to exhibit a resistance between its gate and source.
4. The voltage protection arrangement of claim 2 , comprising at least one electric field region between the at least one floating region and one of:
the emitter region when the self-triggered transistor means comprises bipolar transistor means, and
the source region when the self-triggered transistor means comprises MOS transistor means,
wherein the length of the at least one electric field region determines the threshold voltage.
5. The voltage protection arrangement of claim 2 , wherein the at least one floating region is arranged to form, with one of:
the emitter region when the self-triggered transistor means comprises bipolar transistor means, and
the source region when the self-triggered transistor means comprises MOS transistor means
and adjacent semiconductor material, a bipolar transistor.
6. The voltage protection arrangement of claim 1 , wherein the at least one floating region comprises a plurality of floating regions.
7. The voltage protection arrangement of claim 6 , wherein the plurality of floating regions are arranged between alternating:
collector and emitter regions when the self-triggered transistor means comprises bipolar transistor means, and
drain and source regions when the self-triggered transistor means comprises MOS transistor means.
8. The voltage protection arrangement of claim 7 , wherein the self-triggered transistor means comprises one of:
PNP transistor means when said self-triggered transistor means comprises bipolar transistor means, and
PMOS transistor means when said self-triggered transistor means comprises MOS transistor means,
the at least one floating region comprises P+ type material and the arrangement is provided in N− type material.
9. The voltage protection arrangement of claim 1 , wherein the self-triggered transistor means comprises one of:
NPN transistor means when said self-triggered transistor means comprises bipolar transistor means, and
NMOS transistor means when said self-triggered transistor means comprises MOS transistor means,
the at least one floating region comprises N+ type material and the arrangement is provided in P− type material.
10. The voltage protection arrangement of claim 1 , wherein the self-triggered transistor means comprises LDMOS transistor means when said self-triggered transistor means comprises MOS transistor means.
11. A semiconductor device comprising the voltage protection arrangement of claim 1 .
12. A method of voltage protection for use to protect a semiconductor structure from electro-static discharge voltage at an input node thereof, the method comprising:
providing discharge means, having an input coupled to the input node, and an output coupled to ground, the discharge means providing a discharge path from the input node to ground if the voltage at the input node exceeds a threshold voltage,
wherein the discharge means comprises self-triggered transistor means having one of:
collector and emitter regions if said self-triggered transistor means comprises bipolar transistor means, and
drain and source regions if said self-triggered transistor means comprises MOS transistor means, and
at least one floating region therein arranged to modify a threshold voltage by separating an electric field between one of:
the collector and emitter regions when the self-triggered transistor means comprises bipolar transistor means, and
the drain and source regions when the self-triggered transistor means comprises MOS transistor means.
13. The method of voltage protection of claim 12 wherein one of:
when the self-triggered transistor means comprises bipolar transistor means, the bipolar transistor means has a grounded base, and
when the self-triggered transistor means comprises MOS transistor means, the MOS transistor means has a grounded gate.
14. The method of voltage protection of claim 12 wherein, when the self-triggered transistor means comprises MOS transistor means, the MOS transistor means is arranged to exhibit a resistance between its gate and source.
15. The method of voltage protection of claim 13 , further comprising providing at least one electric field region between the at least one floating region and one of:
the emitter region when the self-triggered transistor means comprises bipolar transistor means, and
the source region when the self-triggered transistor means comprises MOS transistor means,
wherein the length of the at least one electric field region determines the threshold voltage.
16. The method of voltage protection of claim 13 , wherein the at least one floating region forms, with one of:
the emitter region when the self-triggered transistor means comprises bipolar transistor means, and
the source region when the self-triggered transistor means comprises MOS transistor means
and adjacent semiconductor material, a bipolar transistor.
17. The method of voltage protection of claim 12 , wherein the at least one floating region comprises a plurality of floating regions.
18. The method of voltage protection of claim 17 , wherein the plurality of floating regions are provided between alternating:
collector and emitter regions when the self-triggered transistor means comprises bipolar transistor means, and
drain and source regions when the self-triggered transistor means comprises bipolar transistor means.
19. The method of voltage protection of claim 12 , wherein the self-triggered transistor means comprises one of:
PNP transistor means when said said self-triggered transistor means comprises bipolar transistor means, and
PMOS transistor means when said self-triggered transistor means comprises MOS transistor means, the at least one floating region comprises P+ type material and the arrangement is provided in N− type material.
20. The method of voltage protection of claims 12 , wherein the self-triggered transistor means comprises one of:
NPN transistor means when said said self-triggered transistor means comprises bipolar transistor means, and
NMOS transistor means when said self-triggered transistor means comprises MOS transistor means, the at least one floating region comprises N+ type material and the arrangement is provided in P− type material.
21. The method of voltage protection of claim 12 , wherein the self-triggered transistor means comprises LDMOS transistor means when said self-triggered transistor means comprises MOS transistor means.
22. The method of voltage protection of claim 12 , performed in a semiconductor device.