IP Library Granted Patent US 7,049,930
Granted Patent B2
US 7,049,930 · App. 10/663,354 · Granted May 23, 2006

Arrangement of several resistors jointly positioned in a well of a semiconductor device, and a semiconductor device including at least one such arrangement

Assignee: Infineon Technologies AG
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Quick Facts
Patent No.
US 7,049,930
App. No.
10/663,354
Granted
May 23, 2006
Kind
B2
Abstract

An arrangement of several resistors jointly positioned in one and the same well of a semiconductor device, as well as to a semiconductor device including at least one such arrangement of resistors, wherein the resistors, when viewed in a longitudinal direction of the resistors, are displaced in relation to one another.

Claims (22)

1. An arrangement of several resistors comprising: the resistors jointly positioned in one and the same well of a semiconductor device, wherein each of the resistors are extending in a longitudinal direction and are spaced laterally from each other and wherein each of the resistors is alternately displaced toward opposite sides of the well in the longitudinal direction of the resistors in relation to an adjacent resistor, the arrangement configured to reduce coupling between said resistors.

2. The arrangement according to claim 1 , wherein the resistors all have substantially the same length.

3. The arrangement according to claim 1 , wherein the resistors all have substantially the same breadth or width, respectively.

4. The arrangement according to claim 1 , wherein the resistors all have substantially the same depth.

5. The arrangement according to claim 1 , wherein the resistors all are of substantially identical structure.

6. The arrangement according to claim 1 , wherein the resistors all have substantially the same individual resistance value.

7. The arrangement according to claim 1 , wherein each of the resistors is displaced in the longitudinal direction of the resistors such that substantially none of a first resistor overlaps with an adjacent resistor.

8. The arrangement according to claim 1 , said arrangement comprising at least five resistors.

9. The arrangement according to claim 1 , wherein a distance between a first resistor of said resistors and a second resistor of said resistors, when viewed in a transverse direction of the resistors, is smaller than one fifth of a length of said first resistor or of said second resistor, respectively.

10. The arrangement according to claim 1 , wherein a first resistor of said resistors is displaced approximately a length of a second resistor of said resistors, wherein said first resistor is adjacent to said second resistor.

11. The arrangement according to claim 1 , wherein a distance between a first resistor of said resistors and a second resistor of said resistors, when viewed in a transverse direction of the resistors, is smaller than one third of a breadth or width, of said first resistor or of said second resistor, respectively.

12. The arrangement according to claim 1 , wherein a distance between a first resistor of said resistors and a second resistor of said resistors, when viewed in a transverse direction of the resistors, is smaller than one fifth of a breadth or width of said first resistor or of said second resistor, respectively.

13. The arrangement according to claim 1 , wherein the well is relatively weakly n-doped.

14. The arrangement according to claim 1 , wherein the resistors are relatively strongly n-doped.

15. The arrangement according to claim 14 , wherein the resistors are n-diffusion resistors.

16. The arrangement according to claim 1 , wherein the resistors are connected to corresponding signal driver devices of the semiconductor device.

17. The arrangement according to claim 1 , wherein the resistors are connected to corresponding output pads of the semiconductor device.

18. The arrangement according to claim 1 , wherein the resistors are connected in parallel.

19. The arrangement according to claim 18 , wherein the resistors are connected in parallel such that a total resistance value results for the resistors connected in parallel which corresponds to a desired resistance value.

20. The arrangement according to claim 19 , wherein the resistors connected in parallel are jointly connected to a particular signal driver device, and wherein the desired resistance value corresponds to a resistance value desired for the corresponding signal driver device.

21. A semiconductor device comprising: an arrangement of resistors, the arrangement includes the resistors jointly positioned in one and the same well of a semiconductor device, wherein each of the resistors are extending in a longitudinal direction, and are spaced laterally from each other and wherein each of the resistors is alternately displaced toward opposite sides of the well in the longitudinal direction of the resistors in relation to an adjacent resistor, the arrangement configured to reduce coupling between said resistors.

22. The arrangement according to claim 1 , wherein a distance between a first resistor of said resistors and a second resistor of said resistors, when viewed in a transverse direction of the resistors, is smaller than one third of a length of said first resistor or of said second resistor, respectively.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT 7105729 PREVIOUSLY RECORDED AT REEL: 036827 FRAME: 0885. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 26, 2017
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 043336/0694 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036827/0885 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023796/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2004
From: SCHNABEL, JOACHIM; SCHAEFER, ANDRE; OBERGRUSSBERGER, XAVER; MOSLER, SEBASTIAN
To: INFINEON TECHNOLOGIES AG
Reel/Frame 014988/0481 →
Priority Claims (1)
DE 102 43 604 · Sep 19, 2002 · national
Continuity (1)
Related Publication 20040130433A1 · Jul 8, 2004