IP Library Granted Patent US 6,940,320
Granted Patent B2
US 6,940,320 · App. 10/685,094 · Granted Sep 6, 2005

Power control system startup method and circuit

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Quick Facts
Patent No.
US 6,940,320
App. No.
10/685,094
Granted
Sep 6, 2005
Kind
B2
Abstract

A power control system uses two separate currents to control a startup operation of the power control system. One of the currents has a small value and is used to charge an output voltage to an initial value. Once the initial value is reached, a second current that has a large value is used to charge the output voltage to an operating voltage value.

Claims (37)

1. A power control system startup method comprising:

coupling a high voltage device to receive an input voltage and responsively generate a bias current and couple the bias current to an output transistor of the high voltage device;

coupling a switch element to shunt the bias current away from the output transistor when an output voltage is less than a first value; and

coupling the bias current to a control electrode of the output transistor of the high voltage device to generate an output current that is greater than the bias current when the output voltage is greater than the first value.

2. A power control system startup method comprising:

coupling a high voltage device to receive an input voltage and responsively generate a bias current and couple the bias current to an output transistor of the high voltage device including coupling a first current carrying electrode of a J-FET transistor to receive the input voltage, coupling a second current carrying electrode of the J-FET transistor to a first current carrying electrode of the output transistor, coupling a resistor to receive the bias current from the second current carrying electrode of the J-FET transistor and to couple the bias current to a control electrode of the output transistor;

coupling a switch element to shunt the bias current away from the output transistor when an output voltage is less than a first value; and

coupling the output transistor of the high voltage device to generate an output current that is greater than the bias current when the output voltage is greater than the first value.

3. The method of claim 2 wherein coupling the switch element to shunt the bias current away from the output transistor when the output voltage is less than the first value includes coupling a pinch resistor to shunt the bias current away from the output transistor.

4. The method of claim 3 wherein coupling the pinch resistor to shunt the bias current away from the output transistor includes coupling a first terminal of the pinch resistor to the control electrode of the output transistor and a second terminal to an output for forming the output voltage.

5. The method of claim 2 wherein coupling the switch element to shunt the bias current away from the output transistor when the output voltage is less than the first value includes coupling a comparator coupled MOS transistor to shunt the bias current away from the output transistor.

6. The method of claim 5 wherein coupling the comparator coupled MOS transistor to shunt the bias current away from the output transistor includes coupling a first current carrying electrode of the comparator coupled MOS transistor to the control electrode of the output transistor, coupling a second carrying electrode of the comparator coupled MOS transistor to an output, and coupling a control electrode of the comparator coupled MOS transistor to receive a reference voltage.

7. The method of claim 6 further including stacking two threshold adjusted MOS transistors to form the reference voltage.

8. A power control system startup method comprising:

receiving an input voltage;

generating a first current from the input voltage;

shunting the first current to an output of the startup circuit;

using the first current to form an output voltage at the output of the startup circuit; and

coupling a second current from an output of an output transistor to the output of the startup circuit to form the output voltage after the output voltage is greater than a first value wherein the second current is greater than the first current.

9. The method of claim 8 wherein coupling the second current from the output of the output transistor to the output of the startup circuit to form the output voltage at the output of the startup circuit includes coupling a bias current to the output transistor of the startup circuit after the output voltage is greater than the first value.

10. The method of claim 8 wherein shunting the first current to the output of the startup circuit includes enabling a comparator transistor to couple the first current to the output of the startup circuit.

11. The method of claim 8 further including coupling the output to a voltage return to disable the power control system.

12. A power control system startup method comprising:

receiving an input voltage;

generating a first current from the input voltage;

shunting the first current to an output of a startup circuit including enabling a pinch resistor to couple the first current to the output of the startup circuit;

using the first current to form an output voltage at the output of the startup circuit; and

using a second current to form the output voltage when the output voltage is greater than a first value wherein the second current is greater than the first current.

13. The method of claim 12 wherein enabling the pinch resistor to couple the first current to the output of the startup circuit includes coupling the pinch resistor between the output of the startup circuit and a control electrode of an output transistor of the startup circuit, and enabling the pinch resistor when the output voltage is less than a pinch-off voltage of the pinch resistor.

14. A power control system method comprising:

generating a first output current at an output of a startup circuit responsively to a first value of an output voltage at the output of the startup circuit; and

coupling the output of the startup circuit to a voltage return to shunt the output current to the voltage return and disable the output voltage.

15. The method of claim 14 wherein generating the first output current at the output of the startup circuit responsively to the first value of the output voltage includes coupling a bias current to the output of the startup circuit and disabling an output transistor of the startup circuit.

16. The method of claim 15 wherein coupling the bias current to the output of the startup circuit and disabling the output transistor of the startup circuit includes shunting the bias current from a control electrode of the output transistor to the output of the startup circuit.

17. The method of claim 16 wherein shunting the bias current from the control electrode of the output transistor to the output of the startup circuit includes enabling a pinch resistor to shunt the bias current.

18. The method of claim 15 wherein generating the first output current at the output of the startup circuit responsively to the first value of the output voltage includes enabling the output transistor to generate the first output current.

19. The method of claim 18 wherein enabling the output transistor to generate the first output current includes coupling a J-FET transistor to a high voltage input to generate a bias current, and coupling the bias current to the output transistor to enable the output transistor.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038631/0345 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A. (ON ITS BEHALF AND ON BEHALF OF ITS PREDECESSOR IN INTEREST, CHASE MANHATTAN BANK)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038632/0074 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2005
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 016183/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2003
From: SUKUP, FRANTISEK; HALAMIK, JOSEF; HALL, JEFFERSON W.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C.
Reel/Frame 014612/0617 →