IP Library Granted Patent US 7,170,125
Granted Patent B2
US 7,170,125 · App. 10/724,134 · Granted Jan 30, 2007

Capacitor with electrodes made of ruthenium and method for patterning layers made of ruthenium or ruthenium

Assignee: Infineon Technologies AG
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Quick Facts
Patent No.
US 7,170,125
App. No.
10/724,134
Granted
Jan 30, 2007
Kind
B2
Abstract

A method for patterning layers made of ruthenium or ruthenium(IV) oxide and a capacitor comprising at least one electrode which is constructed from ruthenium or ruthenium(IV) oxide at least in sections. A layer made of ruthenium or ruthenium(IV) oxide is deposited on a substrate and said layer is subsequently covered with a covering layer at least in sections. Through heat treatment of the construction thus obtained in an oxygen atmosphere, the ruthenium is converted into RuO 4 in the uncovered sections and removed by sublimation. The method enables the simple patterning of layers made of ruthenium or ruthenium(IV) oxide and the construction of complex structures, such as trench capacitors, for example.

Claims (24)

1. A capacitor having a first electrode plate and a second electrode plate and a layer made of a dielectric formed between the first electrode plate and the second electrode plate, wherein the second electrode plate is formed from at least a layer made of ruthenium or ruthenium(IV) oxide and a layer made of polysilicon, wherein the capacitor is formed as a trench capacitor in a semiconductor substrate, in which the first electrode plate is formed as a doped section of the semiconductor substrate in a trench wall.

2. The capacitor of claim 1 , wherein the first electrode plate is at least one of supplemented by a layer made of metal or made of an electrically highly conductive material arranged on doped sections.

3. The capacitor of claim 1 , wherein the capacitor is formed as a trench capacitor in a semiconductor substrate and wherein an insulation section is provided in the upper region of a trench wall adjoining an opening of the trench capacitor.

4. The capacitor of claim 1 , wherein at least one of the electrode plates is formed from ruthenium.

5. The capacitor of claim 1 , wherein at least one of the electrode plates is formed from ruthenium(IV) oxide.

6. A capacitor having a first electrode plate and a second electrode plate and a layer made of a dielectric formed between the first electrode plate and the second electrode plate, wherein at least a portion of one of the electrode plates is formed from ruthenium or ruthenium(IV) oxide, wherein the capacitor is formed as a trench capacitor in a semiconductor substrate, and wherein an insulation section is provided in an upper region of a trench wall adjoining an opening of the trench capacitor, wherein the first electrode plate is formed as a doped section of the semiconductor substrate in the trench wall and the second electrode plate is formed at least in part from ruthenium or ruthenium(IV) oxide.

7. The capacitor of claim 6 , further comprising a barrier layer disposed between the layer made of a dielectric and the second electrode plate.

8. The capacitor of claim 6 , wherein the second electrode plate is further formed from a layer made of polysilicon.

9. The capacitor of claim 8 , further comprising a first barrier layer disposed between the ruthenium or ruthenium(IV) oxide and the layer made of polysilicon.

10. The capacitor of claim 9 , further comprising a second barrier layer disposed between the layer made of a dielectric and the second electrode plate.

11. The capacitor of claim 6 , wherein the first electrode plate is at least one of supplemented by a layer made of metal or made of an electrically highly conductive material arranged on the doped sections.

12. The capacitor of claim 6 , wherein at least one of the electrode plates is formed from ruthenium.

13. The capacitor of claim 6 , wherein at least one of the electrode plates is formed from ruthenium(IV) oxide.

14. A capacitor having a first electrode plate and a second electrode plate and a layer made of a dielectric formed between the first electrode plate and the second electrode plate, wherein the second electrode plate is formed from at least a layer made of ruthenium or ruthenium(IV) oxide and a layer made of polysilicon, wherein the capacitor is formed as a trench capacitor in a semiconductor substrate, in which the first electrode plate is formed as a doped section of the semiconductor substrate in a trench wall, the capacitor further comprising a barrier layer between the layer made of ruthenium or ruthenium(IV) oxide and the layer made of polysilicon.

15. A capacitor comprising:

a first electrode that includes a first sidewall, a bottom surface and a second sidewall, the first sidewall, the bottom surface and the second sidewall forming an enclosure;

a dielectric layer overlying the first sidewall, the bottom surface and the second sidewall;

a metal layer overlying the dielectric layer and lining the first sidewall, the bottom surface and the second sidewall, the metal layer comprising ruthenium or ruthenium(IV) oxide; and

at least one material overlying the metal layer and filling at least a portion of the enclosure, wherein the at least one material comprises polysilicon.

16. The capacitor of claim 15 , further comprising:

a first barrier layer between the dielectric layer and the metal layer; and

a second barrier layer between the metal layer and the at least one material.

17. The capacitor of claim 15 , wherein the first electrode comprises doped silicon.

18. The capacitor of claim 17 , wherein the capacitor comprises a trench capacitor, wherein the doped silicon is formed along sidewalls of a trench formed in a silicon body, wherein the dielectric layer and the metal layer line the sidewalls of the trench, and wherein the at least one material comprises a conductive layer that fills at least a portion of the trench.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036873/0758 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023796/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 9, 2005
From: SEIDL, HARALD; GUTSCHE, MARTIN
To: INFINEON TECHNOLOGIES AG
Reel/Frame 015690/0211 →
Priority Claims (1)
DE 102 55 841 · Nov 29, 2002 · national
Continuity (1)
Related Publication 20040152255A1 · Aug 5, 2004