Memory module and method for operating a memory module in a data memory system

1. A memory module for operation in a data memory system, comprising:

a plurality of DRAM devices for storing user data; and

a buffer and error checking module, which integrates in a common device housing:

a buffer device connected to the DRAM devices via data lines, and serving to condition data signals being transferred on the data lines between the DRAM devices and a memory control device of the data memory system; and

a DRAM device for storing redundancy data operable to detect and to correct erroneous user data.

2. The memory module of claim 1 , wherein the buffer and error checking module is connected to an even number of DRAM devices for storing the user data.

3. The memory module of claim 2 , wherein the DRAM devices are arranged symmetrically with respect to the buffer and error checking module.

4. The memory module of claim 1 , wherein the buffer and error checking module comprises has an error detecting unit operable,

during a transfer of user data to the memory module, to form and to store the redundancy data; and

during a transfer of user data to the memory control device, to form check data from the user data to be transferred, and also to compare respectively corresponding redundancy data with the check data.

5. The memory module of claim 4 , wherein the buffer and error checking module comprises an error correction unit operable to correct erroneous user data on the basis of respectively corresponding redundancy data and check data.

6. The memory module of claim 5 , wherein the memory module is absent a contact device assigned to a data line for transferring redundancy data.

7. The memory module of claim 5 , wherein the memory module comprises an error signaling unit operable to transfer information on error events to the memory control device.

8. The memory module of claim 5 , wherein the buffer and error checking module has an error evaluation unit operable to identify and to mask out defective memory cells in the DRAM devices.

9. The memory module of claim 1 , wherein the DRAM devices comprise in each case a DDR interface.

10. The memory module of claim 1 , wherein the maximum dimensions of the memory module are about 1.2 inches×5.25 inches.

11. A buffer and error checking module for memory modules, the memory modules comprising in each case a plurality of DRAM devices operated in data memory systems, the buffer and error checking module comprising:

connecting devices;

a buffer/redriver formed in a semiconductor substrate and operable to condition data signals that are transferred to and from the memory modules; and

a memory cell array formed in the semiconductor substrate as an error data memory.

12. The buffer and error checking module of claim 11 , further comprising an error detecting unit operable,

during a transfer of user data to the memory module, to form and to store redundancy data and,

during a transfer of user data to a memory control device of the data memory system, to compare the stored redundancy data with check data formed from the data to be transferred.

13. The buffer and error checking module of claim 12 , further comprising an error correction unit operable to correct erroneous user data on the basis of respectively corresponding redundancy data and check data.

14. The buffer and error checking module of claim 12 , further comprising an error signaling unit operable to transfer information on error events to the data memory system.

15. The buffer and error checking module of claim 12 , further comprising an error evaluation unit operable to identify and to mask out defective memory cells in the DRAM devices connected to the buffer and error checking module.

16. A method for operating a memory module having a plurality of DRAM devices for storing data and at least one buffer and error checking module in a data memory system, the method comprising:

receiving data signals of user data transferred to the memory module and conditioning the data signals with the buffer and error checking module;

forming, in the buffer and error checking module, a corresponding set of redundancy data with respect to the user data;

storing the user data in the DRAM devices;

storing the respectively corresponding set of redundancy data in the buffer and error checking module;

forming in the buffer and error checking module, during a transfer of stored user data from the DRAM devices to a memory control device of the data memory system, a corresponding set of check data;

detecting, through a comparison of respectively corresponding redundancy data and check data, data errors that have occurred in the user data and correcting any such errors on a case by case basis; and

transferring corrected user data to the memory control device.

17. The method of claim 16 , further comprising signaling an occurrence of a data error in the user data to the memory control device of the data memory system.

18. The method of claim 16 , further comprising optimizing a data memory system by:

providing a redundancy bus system for transferring user data and redundancy data in precursor systems on a system board between a memory control device and the memory module;

registering transfer errors in the bus system and analyzing, in the precursor systems, the transfer errors by the memory control device with the aid of the redundancy bus system;

developing, on the basis of an analysis of transfer errors occurring between the memory control device and the memory module, a bus system for transferring the user data of respective precursor systems in a direction of a minimum number of transfer errors; and

providing the data memory system with the bus system developed for a minimum number of transfer errors.