IP Library Granted Patent US 7,459,781
Granted Patent B2
US 7,459,781 · App. 10/725,933 · Granted Dec 2, 2008

Fan out type wafer level package structure and method of the same

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Quick Facts
Patent No.
US 7,459,781
App. No.
10/725,933
Granted
Dec 2, 2008
Kind
B2
Abstract

To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure.

Claims (45)

1. A fan out type wafer level package structure, comprising:

a base;

an adhesion material formed on said base;

a die having a plurality of pads on a top surface that is opposite a bottom surface which is on said adhesion material;

a first dielectric layer formed on said base and filled in a space except said die on said base, wherein the first dielectric layer includes silicone rubber, epoxy, resin or BCB to act as a buffer layer to release stress;

a second dielectric layer formed on said first dielectric layer and said die, wherein said second dielectric layer including a plurality of openings for contact with said plurality of pads;

a contact conductive layer formed on said plurality of pads of said die and within said openings to electrically couple with said pads, respectively;

a plurality of conductive lines formed on said second dielectric layer and in contact with, said contact conductive layer and substantially filling said openings, and said conductive lines being extended out from corresponding said contact conductive layer to corresponding end points;

an isolation layer formed on said conductive lines and said second dielectric layer; and

solder balls passing through said isolation layer welded on said conductive lines for coupling with said conductive lines, respectively.

2. The package structure in claim 1 , wherein surfaces of said first dielectric layer and said die are at the same level.

3. The package structure in claim 1 , wherein said contact conductive layer comprises Ti, Cu, and the combination thereof.

4. The package structure in claim 1 , wherein said conductive lines comprise Ni, Cu, Au, and the combination thereof.

5. The package structure in claim 1 , wherein a material of said base is glass, silicon, ceramic, or crystal material.

6. The package structure in claim 1 , further comprising an epoxy layer formed on a back surface of the base.

7. The package structure in claim 1 , wherein said isolation layer comprises epoxy, resin, and the combination thereof.

8. The package structure in claim 1 , wherein said die is a sawed die and adhered on said base by a picking and placing system.

9. The package structure in claim 1 , wherein said adhesion material include thermally conductive material.

10. A fan out type wafer level package structure, comprising:

a base;

an adhesion material formed on said base;

a die having a plurality of pads on top surface that is opposite to a bottom surface which is on said adhesion material;

a buffer layer formed on said base and adjacent to said die to release stress, wherein said buffer layer includes silicone rubber, epoxy, resin or BCB;

a dielectric layer formed on said buffer layer and said die, wherein said dielectric layer including a plurality of openings;

a contact conductive layer formed on said plurality of pads of said die and within said openings to electrically couple with said pads, respectively;

a plurality of conductive lines formed on said dielectric layer and in contact with, said contact layer and substantially filling said openings, and said conductive lines being extended out from corresponding said contact conductive layer to corresponding end points, wherein said corresponding end points are located inside a surface of said dielectric layer;

an isolation layer formed on said conductive lines and said dielectric layer; and

solder balls passing through said isolation layer welded on said conductive lines for coupling with said conductive lines, respectively.

11. The package structure in claim 10 , wherein said contact layer includes Ti and Cu.

12. The package structure in claim 10 , wherein said conductive lines include Cu, Ni and Au.

13. The package structure in claim 10 , wherein said adhesion material include thermally conductive material.

14. A fan out type wafer level package structure, comprising:

a base;

an adhesion material formed said base;

a die having a plurality of pads on top surface that is opposite to a bottom surface which is on said adhesion material;

a buffer layer formed on said base and adjacent to said die to release stress, wherein said buffer layer includes silicone rubber, epoxy, resin or BCB;

a dielectric layer formed on said buffer layer and said die, wherein said dielectric layer including a plurality of openings;

a contact conductive layer formed on said plurality of pads of said die and within said openings to electrically couple with said pads, respectively, wherein said contact layer includes Ti and Cu;

a plurality of conductive lines formed on said dielectric layer and in contact with, said contact layer and substantially filling said openings, and said conductive lines being extended out from corresponding said contact conductive layer to corresponding end points, wherein said corresponding end points are located inside a surface of said dielectric layer, wherein said conductive lines include Cu, Ni and Au;

an isolation layer formed on said conductive lines and said dielectric layer; and

solder balls passing through said isolation layer welded on said conductive lines for coupling with said conductive lines, respectively.

15. The package structure in claim 14 , wherein said adhesion material include thermally conductive material.

16. The package structure in claim 1 , wherein said first dielectric layer comprises silicone rubber.

17. The package structure in claim 10 , wherein said buffer layer comprises silicone rubber.

18. The package structure in claim 14 , wherein said buffer layer comprises silicone rubber.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 27, 2023
From: ADL ENERGY CORP.
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 065957/0661 →
MERGER Recorded Sep 15, 2023
From: ADL ENGINEERING INC.; ADVANCED CHIP ENGINEERING TECHNOLOGY INC.
To: ADL ENGINEERING INC.
Reel/Frame 064926/0845 →
CHANGE OF NAME Recorded Sep 15, 2023
From: ADL ENGINEERING INC.
To: ADL ENERGY CORP.
Reel/Frame 064927/0462 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2009
From: YANG, WEN-KUN
To: ADVANCED CHIP ENGINEERING TECHNOLOGY INC.
Reel/Frame 022868/0528 →
LEGAL DOCUMENTS LISTED ON APPENDIX A Recorded Jan 9, 2009
From: YANG, WEN-KUN
To: ADVANCED CHIP ENGINEERING TECHNOLOGY INC.
Reel/Frame 022086/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2004
From: ADVANCED CHIP ENGINEERING TECHNOLOGY INC.
To: WEN-KUN YANG
Reel/Frame 014362/0508 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 22, 2004
From: YANG, WEN-KUN; YANG, WEN-PIN; CHEN, SHIH-LI
To: ADVANCED CHIP ENGINEERING TECHNOLOGY INC.
Reel/Frame 014279/0151 →